arch: arm: mpu: Make XN bit conditional on CONFIG_XIP for RAM region
Make the execute never (XN) bit conditonal on CONFIG_XIP for the RAM MPU region attribute. This is required because when CONFIG_XIP is not set, the entire image will be linked into SRAM. In this case, SRAM must be executable. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
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2 changed files with 12 additions and 2 deletions
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@ -110,10 +110,15 @@
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#define REGION_4G REGION_SIZE(4GB)
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/* Some helper defines for common regions */
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/* On Cortex-M, we can only set the XN bit when CONFIG_XIP=y. When
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* CONFIG_XIP=n, the entire image will be linked to SRAM, so we need to keep
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* the SRAM region XN bit clear or the application code will not be executable.
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*/
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#define REGION_RAM_ATTR(size) \
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{ \
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(NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | \
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MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \
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IF_ENABLED(CONFIG_XIP, (MPU_RASR_XN_Msk |)) size | P_RW_U_NA_Msk) \
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}
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#define REGION_RAM_NOCACHE_ATTR(size) \
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{ \
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@ -245,9 +245,14 @@
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.r_limit = limit - 1, \
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}
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#else
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/* On Cortex-M, we can only set the XN bit when CONFIG_XIP=y. When
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* CONFIG_XIP=n, the entire image will be linked to SRAM, so we need to keep
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* the SRAM region XN bit clear or the application code will not be executable.
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*/
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#define REGION_RAM_ATTR(base, size) \
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{\
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.rbar = NOT_EXEC | \
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.rbar = IF_ENABLED(CONFIG_XIP, (NOT_EXEC |)) \
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P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
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/* Cache-ability */ \
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.mair_idx = MPU_MAIR_INDEX_SRAM, \
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