boards: s32z270dc2_r52: add docs
Document supported features and basic how-to for s32z270dc2_r52 boards. Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
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Manuel Arguelles
Carles Cufí
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boards/arm/s32z270dc2_r52/doc/index.rst
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boards/arm/s32z270dc2_r52/doc/index.rst
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.. _s32z270dc2_r52:
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NXP X-S32Z27X-DC (DC2)
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######################
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Overview
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********
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The X-S32Z27X-DC (DC2) board is based on the NXP S32Z270 Real-Time Processor,
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which includes two Real-Time Units (RTU) composed of four ARM Cortex-R52 cores
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each, with flexible split/lock configurations.
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There is one Zephyr board per RTU:
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- ``s32z270dc2_rtu0_r52``, for RTU0
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- ``s32z270dc2_rtu1_r52``, for RTU1.
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Hardware
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********
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Information about the hardware and design resources can be found at
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`NXP S32Z2 Real-Time Processors website`_.
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Supported Features
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==================
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The boards support the following hardware features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| GIC | on-chip | interrupt_controller |
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+-----------+------------+-------------------------------------+
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| ARM Timer | on-chip | timer |
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+-----------+------------+-------------------------------------+
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| SIUL2 | on-chip | pinctrl |
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| | | |
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| | | gpio |
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+-----------+------------+-------------------------------------+
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| LINFlexD | on-chip | serial |
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+-----------+------------+-------------------------------------+
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Other hardware features are not currently supported by the port.
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Connections and IOs
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===================
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The SoC's pads are grouped into ports and pins for consistency with GPIO driver
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and the HAL drivers used by this Zephyr port. The following table summarizes
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the mapping between pads and ports/pins. This must be taken into account when
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using GPIO driver or configuring the pinmuxing for the device drivers.
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+-------------------+-------------+
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| Pads | Port/Pins |
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+===================+=============+
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| PAD_000 - PAD_015 | PA0 - PA15 |
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+-------------------+-------------+
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| PAD_016 - PAD_030 | PB0 - PB14 |
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+-------------------+-------------+
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| PAD_031 | PC15 |
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+-------------------+-------------+
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| PAD_032 - PAD_047 | PD0 - PD15 |
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+-------------------+-------------+
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| PAD_048 - PAD_063 | PE0 - PE15 |
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+-------------------+-------------+
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| PAD_064 - PAD_079 | PF0 - PF15 |
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+-------------------+-------------+
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| PAD_080 - PAD_091 | PG0 - PG11 |
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+-------------------+-------------+
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| PAD_092 - PAD_095 | PH12 - PH15 |
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+-------------------+-------------+
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| PAD_096 - PAD_111 | PI0 - PI15 |
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+-------------------+-------------+
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| PAD_112 - PAD_127 | PJ0 - PJ15 |
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+-------------------+-------------+
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| PAD_128 - PAD_143 | PK0 - PK15 |
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+-------------------+-------------+
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| PAD_144 - PAD_145 | PL0 - PL1 |
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+-------------------+-------------+
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| PAD_146 - PAD_159 | PM2 - PM15 |
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+-------------------+-------------+
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| PAD_160 - PAD_169 | PN0 - PN9 |
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+-------------------+-------------+
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| PAD_170 - PAD_173 | PO10 - PO13 |
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+-------------------+-------------+
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This board does not include user LED's or switches, which are needed for some
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of the samples such as :ref:`blinky-sample` or :ref:`button-sample`.
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Follow the steps described in the sample description to enable support for this
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board.
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System Clock
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============
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The Cortex-R52 cores are configured to run at 800 MHz.
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Serial Port
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===========
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The SoC has 12 LINFlexD instances that can be used in UART mode. Instance 0
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(defined as ``uart0`` in devicetree) is configured for the console and the
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remaining are disabled and not configured.
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Programming and Debugging
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*************************
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Applications for the ``s32z270dc2_rtu0_r52`` and ``s32z270dc2_rtu1_r52`` boards
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can be built in the usual way as documented in :ref:`build_an_application`.
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Currently is only possible to load and execute a Zephyr application binary on
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this board from the internal SRAM, using `Lauterbach TRACE32`_ development
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tools and debuggers.
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.. note::
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Currently, the start-up scripts executed with ``west flash`` and
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``west debug`` commands perform the same steps to initialize the SoC and
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load the application to SRAM. The difference is that ``west flash`` hide the
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Lauterbach TRACE32 interface, executes the application and exits.
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Install Lauterbach TRACE32 Software
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===================================
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Follow the steps described in :ref:`lauterbach-trace32-debug-host-tools` to
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install and set-up Lauterbach TRACE32 software.
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Set-up the Board
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================
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Connect the Lauterbach TRACE32 debugger to the board's JTAG connector (``J134``)
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and to the host computer.
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For visualizing the serial output, connect the board's USB/UART port (``J119``) to
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the host computer and run your favorite terminal program to listen for output.
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For example, using the cross-platform `pySerial miniterm`_ terminal:
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.. code-block:: console
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python -m serial.tools.miniterm <port> 115200
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Replace ``<port>`` with the port where the board can be found. For example,
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under Linux, ``/dev/ttyUSB0``.
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Flashing
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========
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For example, you can build and run the :ref:`hello_world` sample for the board
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``s32z270dc2_rtu0_r52`` with:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: s32z270dc2_rtu0_r52
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:goals: build flash
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You should see the following message in the terminal:
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.. code-block:: console
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Hello World! s32z270dc2_rtu0_r52
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Debugging
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=========
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To enable debugging using Lauterbach TRACE32 software, run instead:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: s32z270dc2_rtu0_r52
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:goals: build debug
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Step through the application in your debugger, and you should see the following
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message in the terminal:
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.. code-block:: console
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Hello World! s32z270dc2_rtu0_r52
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RTU and Core Configuration
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==========================
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This Zephyr port can only run single core in any of the Cortex-R52 cores,
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either in lock-step or split-lock mode. By default, Zephyr runs on the first
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core of the RTU chosen and in lock-step mode (which is the reset
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configuration).
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To build for split-lock mode, the :kconfig:option:`CONFIG_DCLS` must be
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disabled from your application Kconfig file.
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Additionally, to run in a different core or with a different core
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configuration than the default, extra parameters must be provided to the runner
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as follows:
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.. code-block:: console
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west <command> --startup-args elfFile=<elf_path> rtu=<rtu_id> \
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core=<core_id> lockstep=<yes/no>
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Where:
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- ``<command>`` is ``flash`` or ``debug``
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- ``<elf_path>`` is the path to the Zephyr application ELF in the output
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directory
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- ``<rtu_id>`` is the zero-based RTU index (0 for ``s32z270dc2_rtu0_r52``
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and 1 for ``s32z270dc2_rtu1_r52``)
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- ``<core_id>`` is the zero-based core index relative to the RTU on which to
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run the Zephyr application (0, 1, 2 or 3)
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- ``<yes/no>`` can be ``yes`` to run in lock-step, or ``no`` to run in
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split-lock.
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For example, to build the :ref:`hello_world` sample for the board
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``s32z270dc2_rtu0_r52`` with split-lock core configuration:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: s32z270dc2_rtu0_r52
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:goals: build
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:gen-args: -DCONFIG_DCLS=n
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To execute this sample in the second core of RTU0 in split-lock mode:
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.. code-block:: console
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west flash --startup-args elfFile=build/zephyr/zephyr.elf \
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rtu=0 core=1 lockstep=no
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References
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**********
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.. target-notes::
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.. _NXP S32Z2 Real-Time Processors website:
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https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32z-and-s32e-real-time-processors/s32z2-safe-and-secure-high-performance-real-time-processors:S32Z2
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.. _Lauterbach TRACE32:
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https://www.lauterbach.com
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.. _pySerial miniterm:
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https://pyserial.readthedocs.io/en/latest/tools.html#module-serial.tools.miniterm
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