michaelh/zephyr
1
0
Fork 0
Code Releases Activity

x86: paging code rewrite

Browse source 
The x86 paging code has been rewritten to support another paging mode
and non-identity virtual mappings.

 - Paging code now uses an array of paging level characteristics and
   walks tables using for loops. This is opposed to having different
   functions for every paging level and lots of #ifdefs. The code is
   now more concise and adding new paging modes should be trivial.

 - We now support 32-bit, PAE, and IA-32e page tables.

 - The page tables created by gen_mmu.py are now installed at early
   boot. There are no longer separate "flat" page tables. These tables
   are mutable at any time.

 - The x86_mmu code now has a private header. Many definitions that did
   not need to be in public scope have been moved out of mmustructs.h
   and either placed in the C file or in the private header.

 - Improvements to dumping page table information, with the physical
   mapping and flags all shown

 - arch_mem_map() implemented

 - x86 userspace/memory domain code ported to use the new
   infrastructure.

 - add logic for physical -> virtual instruction pointer transition,
   including cleaning up identity mappings after this takes place.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2020-07-04 16:23:32 -07:00 • committed by Anas Nashif
commit 38e17b68e3
26 changed files with 1574 additions and 1751 deletions
Download patch file Download diff file Expand all files Collapse all files

9
arch/x86/core/Kconfig.ia32
View file

@ -76,6 +76,15 @@ config X86_USERSPACE
supporting user-level threads that are protected from each other and
from crashing the kernel.
config X86_PAE
bool "Use PAE page tables"
default y
depends on X86_MMU
help
If enabled, use PAE-style page tables instead of 32-bit page tables.
The advantage is support for the Execute Disable bit, at a cost of
more memory for paging structures.
menu "Architecture Floating Point Options"
depends on CPU_HAS_FPU