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arm: dts: Add DTS support for SAME70 SoC

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Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit is contained in:
Piotr Mienkowski 2017-05-05 22:22:33 +02:00 • committed by Kumar Gala
commit 38d8c863d4
7 changed files with 89 additions and 30 deletions
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30
arch/arm/soc/atmel_sam/same70/Kconfig.defconfig.series
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@ -22,10 +22,6 @@ config SOC_PART_NUMBER
default same70j20 if SOC_PART_NUMBER_SAME70J20 default same70j20 if SOC_PART_NUMBER_SAME70J20
default same70j19 if SOC_PART_NUMBER_SAME70J19 default same70j19 if SOC_PART_NUMBER_SAME70J19
config NUM_IRQ_PRIO_BITS
int
default 3
# #
# SAM E70 family has in total 71 peripherals capable of generating interrupts # SAM E70 family has in total 71 peripherals capable of generating interrupts
# (not all Peripheral Identifiers are used). # (not all Peripheral Identifiers are used).
@ -38,30 +34,4 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
int int
default 300000000 default 300000000
#
# SRAM size and base address
#
config SRAM_BASE_ADDRESS
hex
default 0x20400000
config SRAM_SIZE
int
default 256 if SOC_PART_NUMBER_SAME70Q19 || SOC_PART_NUMBER_SAME70N19 || SOC_PART_NUMBER_SAME70J19
default 384 if SOC_PART_NUMBER_SAME70Q20 || SOC_PART_NUMBER_SAME70N20 || SOC_PART_NUMBER_SAME70J20
default 384 if SOC_PART_NUMBER_SAME70Q21 || SOC_PART_NUMBER_SAME70N21 || SOC_PART_NUMBER_SAME70J21
#
# Flash size and base address
#
config FLASH_BASE_ADDRESS
hex
default 0x00400000
config FLASH_SIZE
int
default 512 if SOC_PART_NUMBER_SAME70Q19 || SOC_PART_NUMBER_SAME70N19 || SOC_PART_NUMBER_SAME70J19
default 1024 if SOC_PART_NUMBER_SAME70Q20 || SOC_PART_NUMBER_SAME70N20 || SOC_PART_NUMBER_SAME70J20
default 2048 if SOC_PART_NUMBER_SAME70Q21 || SOC_PART_NUMBER_SAME70N21 || SOC_PART_NUMBER_SAME70J21
endif # SOC_SERIES_SAME70 endif # SOC_SERIES_SAME70

1
boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig
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@ -14,3 +14,4 @@ CONFIG_SERIAL=y
CONFIG_USART_SAM=y CONFIG_USART_SAM=y
CONFIG_USART_SAM_PORT_1=y CONFIG_USART_SAM_PORT_1=y
CONFIG_BOARD_SAM_E70_XPLAINED=y CONFIG_BOARD_SAM_E70_XPLAINED=y
CONFIG_HAS_DTS=y

1
dts/arm/Makefile
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@ -29,6 +29,7 @@ dtb-$(CONFIG_BOARD_NRF51_BLENANO) = nrf51_blenano.dts_compiled
dtb-$(CONFIG_BOARD_NRF51_PCA10028) = nrf51_pca10028.dts_compiled dtb-$(CONFIG_BOARD_NRF51_PCA10028) = nrf51_pca10028.dts_compiled
dtb-$(CONFIG_BOARD_QUARK_SE_C1000_BLE) = quark_se_c1000_ble.dts_compiled dtb-$(CONFIG_BOARD_QUARK_SE_C1000_BLE) = quark_se_c1000_ble.dts_compiled
dtb-$(CONFIG_BOARD_QEMU_CORTEX_M3) = qemu_cortex_m3.dts_compiled dtb-$(CONFIG_BOARD_QEMU_CORTEX_M3) = qemu_cortex_m3.dts_compiled
dtb-$(CONFIG_BOARD_SAM_E70_XPLAINED) = sam_e70_xplained.dts_compiled
always := $(dtb-y) always := $(dtb-y)
endif endif

30
dts/arm/atmel/same70.dtsi Normal file
View file

@ -0,0 +1,30 @@
/*
* Copyright (c) 2017 Piotr Mienkowski
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <atmel/same70_mem.h>
/ {
cpus {
cpu@0 {
compatible = "arm,cortex-m7";
};
};
flash0: flash {
compatible = "flash";
reg = <0x00400000 DT_FLASH_SIZE>;
};
sram0: memory {
compatible = "sram";
reg = <0x20400000 DT_SRAM_SIZE>;
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};

37
dts/arm/atmel/same70_mem.h Normal file
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@ -0,0 +1,37 @@
#ifndef __DT_BINDING_SAME70_MEM_H
#define __DT_BINDING_SAME70_MEM_H
#define __SIZE_K(x) (x * 1024)
#if defined CONFIG_SOC_PART_NUMBER_SAME70J19
#define DT_FLASH_SIZE __SIZE_K(512)
#define DT_SRAM_SIZE __SIZE_K(256)
#elif defined CONFIG_SOC_PART_NUMBER_SAME70J20
#define DT_FLASH_SIZE __SIZE_K(1024)
#define DT_SRAM_SIZE __SIZE_K(384)
#elif defined CONFIG_SOC_PART_NUMBER_SAME70J21
#define DT_FLASH_SIZE __SIZE_K(2048)
#define DT_SRAM_SIZE __SIZE_K(384)
#elif defined CONFIG_SOC_PART_NUMBER_SAME70N19
#define DT_FLASH_SIZE __SIZE_K(512)
#define DT_SRAM_SIZE __SIZE_K(256)
#elif defined CONFIG_SOC_PART_NUMBER_SAME70N20
#define DT_FLASH_SIZE __SIZE_K(1024)
#define DT_SRAM_SIZE __SIZE_K(384)
#elif defined CONFIG_SOC_PART_NUMBER_SAME70N21
#define DT_FLASH_SIZE __SIZE_K(2048)
#define DT_SRAM_SIZE __SIZE_K(384)
#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q19
#define DT_FLASH_SIZE __SIZE_K(512)
#define DT_SRAM_SIZE __SIZE_K(256)
#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q20
#define DT_FLASH_SIZE __SIZE_K(1024)
#define DT_SRAM_SIZE __SIZE_K(384)
#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q21
#define DT_FLASH_SIZE __SIZE_K(2048)
#define DT_SRAM_SIZE __SIZE_K(384)
#else
#error "Flash and RAM sizes not defined for this chip"
#endif
#endif /* __DT_BINDING_SAME70_MEM_H */

13
dts/arm/sam_e70_xplained.dts Normal file
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@ -0,0 +1,13 @@
/dts-v1/;
#include <atmel/same70.dtsi>
/ {
model = "Atmel SAM E70 Xplained board";
compatible = "atmel,sam_e70_xplained", "atmel,same70q21", "atmel,same70";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
};

7
dts/arm/sam_e70_xplained.fixup Normal file
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@ -0,0 +1,7 @@
/* This file is a temporary workaround for mapping of the generated information
* to the current driver definitions. This will be removed when the drivers
* are modified to handle the generated information, or the mapping of
* generated data matches the driver definitions.
*/
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS