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doc: fix ordered lists in doxygen comments

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doxygen does not support ordered (numbered) lists using reST syntax
``1)`` or ``a)`` unless the doxygen comments are bounded by ``@rst`` and
``@endrst`` markers.  The "doxygen" way to do ordered lists is to use
``-#``.  This PR cleans this up for our API documentation.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
This commit is contained in:
David B. Kinder 2019-11-20 10:12:15 -08:00 • committed by Anas Nashif
commit 38914679f2
3 changed files with 7 additions and 6 deletions
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5
include/arch/arm/arch.h
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@ -154,9 +154,10 @@ extern "C" {
* @brief Define alignment of a stack buffer * @brief Define alignment of a stack buffer
* *
* This is used for two different things: * This is used for two different things:
* 1) Used in checks for stack size to be a multiple of the stack buffer *
* -# Used in checks for stack size to be a multiple of the stack buffer
* alignment * alignment
* 2) Used to determine the alignment of a stack buffer * -# Used to determine the alignment of a stack buffer
* *
*/ */
#define STACK_ALIGN MAX(Z_THREAD_MIN_STACK_ALIGN, Z_MPU_GUARD_ALIGN) #define STACK_ALIGN MAX(Z_THREAD_MIN_STACK_ALIGN, Z_MPU_GUARD_ALIGN)

4
include/arch/x86/ia32/arch.h
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@ -379,8 +379,8 @@ struct k_thread;
* The @a options parameter indicates which floating point register sets * The @a options parameter indicates which floating point register sets
* will be used by the specified thread: * will be used by the specified thread:
* *
* a) K_FP_REGS indicates x87 FPU and MMX registers only * - K_FP_REGS indicates x87 FPU and MMX registers only
* b) K_SSE_REGS indicates SSE registers (and also x87 FPU and MMX registers) * - K_SSE_REGS indicates SSE registers (and also x87 FPU and MMX registers)
* *
* Invoking this routine initializes the thread's floating point context info * Invoking this routine initializes the thread's floating point context info
* to that of an FPU that has been reset. The next time the thread is scheduled * to that of an FPU that has been reset. The next time the thread is scheduled

4
include/sys/arch_interface.h
View file

@ -136,13 +136,13 @@ void arch_cpu_idle(void);
* *
* The requirements for arch_cpu_atomic_idle() are as follows: * The requirements for arch_cpu_atomic_idle() are as follows:
* *
* 1) Enabling interrupts and entering a low-power mode needs to be * -# Enabling interrupts and entering a low-power mode needs to be
* atomic, i.e. there should be no period of time where interrupts are * atomic, i.e. there should be no period of time where interrupts are
* enabled before the processor enters a low-power mode. See the comments * enabled before the processor enters a low-power mode. See the comments
* in k_lifo_get(), for example, of the race condition that * in k_lifo_get(), for example, of the race condition that
* occurs if this requirement is not met. * occurs if this requirement is not met.
* *
* 2) After waking up from the low-power mode, the interrupt lockout state * -# After waking up from the low-power mode, the interrupt lockout state
* must be restored as indicated in the 'key' input parameter. * must be restored as indicated in the 'key' input parameter.
* *
* @see k_cpu_atomic_idle() * @see k_cpu_atomic_idle()