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arm: cmsis: Convert FaultEnable to use direct CMSIS register access

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Jira: ZEP-1568

Change-Id: I1274ee206576babb4bc0b9308d1cc24d7092166a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-01-25 08:45:11 -06:00 • committed by Maureen Helm
commit 388c26574f
2 changed files with 3 additions and 48 deletions
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6
arch/arm/include/cortex_m/exc.h
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@ -85,9 +85,9 @@ static ALWAYS_INLINE void _ExcSetup(void)
NVIC_SetPriority(BusFault_IRQn, _EXC_FAULT_PRIO); NVIC_SetPriority(BusFault_IRQn, _EXC_FAULT_PRIO);
NVIC_SetPriority(UsageFault_IRQn, _EXC_FAULT_PRIO); NVIC_SetPriority(UsageFault_IRQn, _EXC_FAULT_PRIO);
_ScbUsageFaultEnable(); /* Enable Usage, Mem, & Bus Faults */
_ScbBusFaultEnable(); SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
_ScbMemFaultEnable(); SCB_SHCSR_BUSFAULTENA_Msk;
#endif #endif
} }

45
include/arch/arm/cortex_m/scb.h
View file

@ -76,51 +76,6 @@ static inline void _ScbDivByZeroFaultEnable(void)
__scs.scb.ccr.bit.div_0_trp = 1; __scs.scb.ccr.bit.div_0_trp = 1;
} }
/**
*
* @brief Enable usage fault exceptions
*
* This routine enables usage faults.
* By default, the CPU does not raise usage fault exceptions.
*
* @return N/A
*/
static inline void _ScbUsageFaultEnable(void)
{
__scs.scb.shcsr.bit.usgfaultena = 1;
}
/**
*
* @brief Enable bus fault exceptions
*
* This routine enables bus faults.
* By default, the CPU does not raise bus fault exceptions.
*
* @return N/A
*/
static inline void _ScbBusFaultEnable(void)
{
__scs.scb.shcsr.bit.busfaultena = 1;
}
/**
*
* @brief Enable MPU faults exceptions
*
* This routine enables the MPU faults.
* By default, the CPU does not raise MPU fault exceptions.
*
* @return N/A
*/
static inline void _ScbMemFaultEnable(void)
{
__scs.scb.shcsr.bit.memfaultena = 1;
}
/** /**
* *
* @brief Find out if a hard fault is caused by a bus error on vector read * @brief Find out if a hard fault is caused by a bus error on vector read