diff --git a/soc/arm/st_stm32/stm32wba/CMakeLists.txt b/soc/arm/st_stm32/stm32wba/CMakeLists.txt
index ac3ba70ace6..59be7817eab 100644
--- a/soc/arm/st_stm32/stm32wba/CMakeLists.txt
+++ b/soc/arm/st_stm32/stm32wba/CMakeLists.txt
@@ -4,3 +4,7 @@ zephyr_include_directories(${ZEPHYR_BASE}/drivers)
 zephyr_sources(
   soc.c
   )
+
+zephyr_sources_ifdef(CONFIG_PM
+  power.c
+  )
diff --git a/soc/arm/st_stm32/stm32wba/power.c b/soc/arm/st_stm32/stm32wba/power.c
new file mode 100644
index 00000000000..51bc737858a
--- /dev/null
+++ b/soc/arm/st_stm32/stm32wba/power.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2022 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/kernel.h>
+#include <zephyr/pm/pm.h>
+#include <soc.h>
+#include <zephyr/init.h>
+
+#include <stm32wbaxx_ll_utils.h>
+#include <stm32wbaxx_ll_bus.h>
+#include <stm32wbaxx_ll_cortex.h>
+#include <stm32wbaxx_ll_pwr.h>
+#include <stm32wbaxx_ll_rcc.h>
+#include <stm32wbaxx_ll_system.h>
+#include <clock_control/clock_stm32_ll_common.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
+
+void set_mode_stop(uint8_t substate_id)
+{
+	switch (substate_id) {
+	case 1: /* enter STOP0 mode */
+		LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0);
+		break;
+	case 2: /* enter STOP1 mode */
+		LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1);
+		break;
+	default:
+		LOG_DBG("Unsupported power state substate-id %u", substate_id);
+		break;
+	}
+}
+
+void set_mode_standby(uint8_t substate_id)
+{
+	ARG_UNUSED(substate_id);
+	/* Select standby mode */
+	LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
+}
+
+/* Invoke Low Power/System Off specific Tasks */
+__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+	switch (state) {
+	case PM_STATE_SUSPEND_TO_IDLE:
+		set_mode_stop(substate_id);
+		break;
+	case PM_STATE_STANDBY:
+		/* To be tested */
+		set_mode_standby(substate_id);
+		break;
+	default:
+		LOG_DBG("Unsupported power state %u", state);
+		return;
+	}
+
+	/* Set SLEEPDEEP bit of Cortex System Control Register */
+	LL_LPM_EnableDeepSleep();
+
+	/* Select mode entry : WFE or WFI and enter the CPU selected mode */
+	k_cpu_idle();
+}
+
+/* Handle SOC specific activity after Low Power Mode Exit */
+__weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+	switch (state) {
+	case PM_STATE_SUSPEND_TO_IDLE:
+		if (substate_id <= 2) {
+			LL_LPM_DisableSleepOnExit();
+			LL_LPM_EnableSleep();
+		} else {
+			LOG_DBG("Unsupported power substate-id %u",
+							substate_id);
+		}
+	case PM_STATE_STANDBY:
+		/* To be tested */
+		LL_LPM_EnableSleep();
+	case PM_STATE_SOFT_OFF:
+		/* We should not get there */
+		__fallthrough;
+	case PM_STATE_ACTIVE:
+		__fallthrough;
+	case PM_STATE_SUSPEND_TO_RAM:
+		__fallthrough;
+	case PM_STATE_SUSPEND_TO_DISK:
+		__fallthrough;
+	default:
+		LOG_DBG("Unsupported power state %u", state);
+		break;
+	}
+	/* need to restore the clock */
+	stm32_clock_control_init(NULL);
+
+	/*
+	 * System is now in active mode.
+	 * Reenable interrupts which were disabled
+	 * when OS started idling code.
+	 */
+	irq_unlock(0);
+}
+
+/* Initialize STM32 Power */
+static int stm32_power_init(void)
+{
+	/* enable Power clock */
+	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
+
+#ifdef CONFIG_DEBUG
+	/* Enable the Debug Module during all and any Low power mode */
+	LL_DBGMCU_EnableDBGStopMode();
+#endif /* CONFIG_DEBUG */
+
+	return 0;
+}
+
+SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);