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soc: nordic: nrf54h: disable CAN120 MCAN cache

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Configure CAN120 MCAN core registers as non-cachable to prevent D-Cache
from inhibiting volatile accesses to the CAN120 MCAN registers. Also
apply non-cachable attribute to the message ram region. Even though the
MCAN driver handles cache invalidation/flushing, MPU faults are still
triggered (to be investigated).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2024-05-08 12:52:01 +02:00 • committed by Carles Cufí
commit 3731a137e7
1 changed files with 8 additions and 0 deletions
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8
soc/nordic/nrf54h/mpu_regions.c
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@ -10,6 +10,10 @@
#define USBHS_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(usbhs), core)
#define USBHS_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(usbhs), core)
#define CAN120_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(can120), message_ram)
#define CAN120_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), message_ram) + \
DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), m_can)
static struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("FLASH_0",
CONFIG_FLASH_BASE_ADDRESS,
@ -24,6 +28,10 @@ static struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("USBHS_CORE", USBHS_BASE,
REGION_RAM_NOCACHE_ATTR(USBHS_BASE, USBHS_SIZE)),
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(can120), okay)
MPU_REGION_ENTRY("CAN120_MCAN", CAN120_BASE,
REGION_RAM_NOCACHE_ATTR(CAN120_BASE, CAN120_SIZE)),
#endif
};
const struct arm_mpu_config mpu_config = {