From 36f6cafdb09c5f534b0f2f28841ce9de8fa5d48e Mon Sep 17 00:00:00 2001 From: James Roy Date: Thu, 6 Feb 2025 20:00:17 +0800 Subject: [PATCH] dts: bindings: clock: Change the property names in the DTS Rename the following properties in bindings and DTS: -- freqs_mhz => freqs-mhz -- cg_reg => cg-reg -- pll_ctrl_reg => pll-ctrl-reg Signed-off-by: James Roy --- boards/mediatek/mt8195/mt8195_adsp.dts | 6 +++--- dts/bindings/clock/mediatek,mt8195_cpuclk.yaml | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/boards/mediatek/mt8195/mt8195_adsp.dts b/boards/mediatek/mt8195/mt8195_adsp.dts index 76a2b94415a..53346746041 100644 --- a/boards/mediatek/mt8195/mt8195_adsp.dts +++ b/boards/mediatek/mt8195/mt8195_adsp.dts @@ -34,9 +34,9 @@ cpuclk: cpuclk@10000000 { compatible = "mediatek,mt8195_cpuclk"; reg = <0x10000000 380>; - cg_reg = <0x10720180>; - pll_ctrl_reg = <0x1000c7e0>; - freqs_mhz = <26 370 540 720>; + cg-reg = <0x10720180>; + pll-ctrl-reg = <0x1000c7e0>; + freqs-mhz = <26 370 540 720>; }; core_intc: core_intc@0 { diff --git a/dts/bindings/clock/mediatek,mt8195_cpuclk.yaml b/dts/bindings/clock/mediatek,mt8195_cpuclk.yaml index ea85d99580a..75d4cb1ed3e 100644 --- a/dts/bindings/clock/mediatek,mt8195_cpuclk.yaml +++ b/dts/bindings/clock/mediatek,mt8195_cpuclk.yaml @@ -4,13 +4,13 @@ description: MediaTek Audio DSP CPU Frequency Control compatible: "mediatek,mt8195_cpuclk" properties: - freqs_mhz: + freqs-mhz: type: array description: Available frequencies in ascending order required: true reg: type: array - cg_reg: + cg-reg: type: int - pll_ctrl_reg: + pll-ctrl-reg: type: int