spell: fix Kconfig help typos: /arch

Fix misspellings in Kconfig help text

Change-Id: I2a753b57107f09073eb84ac757ac1e180ae89349
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>

arch/arc/Kconfig

@@ -97,7 +97,7 @@ config	RGF_NUM_BANKS
 	register bank, in the set, will be used by FIRQ interrupts.
 	If fast interrupts are supported but there is only 1
 	register bank, the fast interrupt handler must save
-	and restore general purpose regsiters.
+	and restore general purpose registers.
 
 config	FIRQ_STACK_SIZE
 	int

arch/arm/core/cortex_m/Kconfig

@@ -28,7 +28,7 @@ config ISA_THUMB2
 	the Thumb instructions set. This allows more of the application to
 	benefit from the best in class code density of Thumb.
 
-	For performance optimised code Thumb-2 technology uses 31 percent
+	For performance optimized code Thumb-2 technology uses 31 percent
 	less memory to reduce system cost, while providing up to 38 percent
 	higher performance than existing high density code, which can be used
 	to prolong battery-life or to enrich the product feature set. Thumb-2

arch/arm/soc/atmel_sam/same70/Kconfig.series

@@ -17,4 +17,4 @@ config SOC_SERIES_SAME70
 	help
 	Enable support for Atmel SAM E70 ARM Cortex-M7 Microcontrollers.
 	Part No.: SAME70J19, SAME70J20, SAME70J21, SAME70N19, SAME70N20,
-	SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21
+	SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21

arch/arm/soc/atmel_sam3/Kconfig

@@ -23,7 +23,7 @@ config SOC_ATMEL_SAM3_EXT_SLCK
 	adds a few seconds to boot time, as the crystal
 	needs to stabilize after power-up.
 
-	Says n if you do not need accraute and precise timers.
+	Says n if you do not need accurate and precise timers.
 	The slow clock will be driven by the internal fast
 	RC oscillator running at 32 kHz.
 

arch/x86/Kconfig

@@ -119,7 +119,7 @@ config SSE_FP_MATH
 	performing floating point math. This can greatly improve performance
 	when exactly the same operations are to be performed on multiple
 	data objects; however, it can also significantly reduce performance
-	when pre-emptive task switches occur because of the larger register
+	when preemptive task switches occur because of the larger register
 	set that must be saved and restored.
 
 	Disabling this option means that the compiler utilizes only the

arch/x86/soc/intel_quark/quark_se/Kconfig

@@ -42,11 +42,11 @@ config SYS_LOG_ARC_INIT_LEVEL
 
 	- 1 ERROR, only write SYS_LOG_ERR
 
-	- 2 WARNING, write SYS_LOG_WRN in adition to previous level
+	- 2 WARNING, write SYS_LOG_WRN in addition to previous level
 
-	- 3 INFO, write SYS_LOG_INF in adition to previous levels
+	- 3 INFO, write SYS_LOG_INF in addition to previous levels
 
-	- 4 DEBUG, write SYS_LOG_DBG in adition to previous levels
+	- 4 DEBUG, write SYS_LOG_DBG in addition to previous levels
 
 config ARC_GDB_ENABLE
 	bool "Allows the usage of GDB with the ARC processor."
@@ -70,7 +70,7 @@ config QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32
 	int "IPM Console Ring Buffer Size"
 	default 256
 	help
-	Size of the buffer for the console reciever, for incoming
+	Size of the buffer for the console receiver, for incoming
 	console messages from the ARC side. Must be a power of 2.
 endif
 endif

arch/xtensa/Kconfig

@@ -28,8 +28,8 @@ config XTENSA_NO_IPC
 	select ATOMIC_OPERATIONS_C
 	default n
 	help
-	Uncheck this if you core does not implment "SCOMPARE1" register and "s32c1i"
-	isntruction.
+	Uncheck this if you core does not implement "SCOMPARE1" register and "s32c1i"
+	instruction.
 
 config SW_ISR_TABLE
 	bool
@@ -39,7 +39,7 @@ config SW_ISR_TABLE
 	Enable an interrupt handler table implemented in software. This
 	table, unlike ISRs connected directly in the vector table, allow
 	a parameter to be passed to the interrupt handlers. Also, invoking
-	the exeception/interrupt exit stub is automatically done.
+	the exception/interrupt exit stub is automatically done.
 	This has to be enabled for dynamically connecting interrupt handlers
 	at runtime (SW_ISR_TABLE_DYNAMIC).