From 367cd74ed1eb45d2ee146a8b9b01dc54131435b0 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Tue, 2 Apr 2024 10:24:06 +0300 Subject: [PATCH] soc: Add the MAX32657 NS Peripheral This commit adds MAX32657 Non-Secure peripheral support Signed-off-by: Sadik Ozer --- dts/arm/adi/max32/max32657_ns.dtsi | 43 ++++++++++++++++++++++++++++++ soc/adi/max32/Kconfig | 5 ++++ 2 files changed, 48 insertions(+) create mode 100644 dts/arm/adi/max32/max32657_ns.dtsi diff --git a/dts/arm/adi/max32/max32657_ns.dtsi b/dts/arm/adi/max32/max32657_ns.dtsi new file mode 100644 index 00000000000..673ca25b0cf --- /dev/null +++ b/dts/arm/adi/max32/max32657_ns.dtsi @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + soc { + sram: sram@20000000 { + ranges = <0x0 0x20000000 0x40000>; + }; + + peripheral: peripheral@40000000 { + ranges = <0x0 0x40000000 0x10000000>; + + pinctrl: pin-controller@8000 { + ranges = <0x8000 0x40008000 0x1000>; + }; + }; + + flc0: flash_controller@50029000 { + compatible = "adi,max32-flash-controller"; + reg = <0x50029000 0x400>; + + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + flash0: flash@1000000 { + compatible = "soc-nv-flash"; + reg = <0x01000000 DT_SIZE_K(1024)>; + write-block-size = <16>; + erase-block-size = <8192>; + }; + }; + }; +}; + +#include "max32657_common.dtsi" diff --git a/soc/adi/max32/Kconfig b/soc/adi/max32/Kconfig index 63e2d1b4b3e..5750ddb609a 100644 --- a/soc/adi/max32/Kconfig +++ b/soc/adi/max32/Kconfig @@ -68,4 +68,9 @@ config MAX32_SECONDARY_RV32_BOOT_ADDRESS default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_RV32_PARTITION)) depends on MAX32_SECONDARY_RV32 +config BUILD_WITH_TFM + default y if TRUSTED_EXECUTION_NONSECURE + help + Auto set WITH_TFM for a Non-Secure version of the board, + endif # SOC_FAMILY_MAX32