boards: scobc_a1: Change HRMEM and UART definitions

The following changes have been made in the FM (Flight Model) of the
`SC-OBC Module A1`:

  - Change in the UART Core register address
    Link: https://sc-obc-fpga-technical-reference-manual.readthedocs.io/ja/latest/#orgecb2e01

  - Change in the size of HRMEM (High-Reliability Memory)
    Link: https://sc-obc-fpga-technical-reference-manual.readthedocs.io/ja/latest/#orgc3b1ecc

As a result, we have defined the EM board revision as `1.0.0` and the
FM as `2.0.0`. The EM configuration has been moved to
`scobc_a1_1_0_0.overlay`.

Signed-off-by: Takuya Sasaki <takuya.sasaki@spacecubics.com>

boards/sc/scobc_a1/board.yml

@@ -2,5 +2,11 @@ board:
   name: scobc_a1
   full_name: SC-OBC Module A1
   vendor: sc
+  revision:
+    format: major.minor.patch
+    default: 2.0.0
+    revisions:
+      - name: 1.0.0
+      - name: 2.0.0
   socs:
   - name: designstart_fpga_cortex_m3

boards/sc/scobc_a1/scobc_a1.dts

@@ -38,13 +38,13 @@
 	soc {
 		hrmem: memory@0 {
 			compatible = "sc,hrmem";
-			reg = <0x00000000 DT_SIZE_K(128)>;
+			reg = <0x00000000 DT_SIZE_M(4)>;
 		};
 
-		uartlite0: uartlite@50010000 {
+		uartlite0: uartlite@4f010000 {
 			compatible = "xlnx,xps-uartlite-1.00.a";
 			interrupts = <0 0>;
-			reg = <0x50010000 0x10000>;
+			reg = <0x4f010000 0x10000>;
 		};
 	};
 };

boards/sc/scobc_a1/scobc_a1_1_0_0.overlay

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 Space Cubics Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &hrmem;
+/delete-node/ &uartlite0;
+
+/ {
+	soc {
+		hrmem: memory@0 {
+			compatible = "sc,hrmem";
+			reg = <0x00000000 DT_SIZE_K(128)>;
+		};
+
+		uartlite0: uartlite@50010000 {
+			compatible = "xlnx,xps-uartlite-1.00.a";
+			interrupts = <0 0>;
+			reg = <0x50010000 0x10000>;
+		};
+	};
+};