espi: it8xxx2: enable configuration of Chromebook
This enables the below configuration so the AP and EC are able to communicate over eSPI: CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit is contained in:
Dino Li
Anas Nashif
parent
f3c1acaeea
commit
36164c29c1
8 changed files with 434 additions and 7 deletions
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@ -21,6 +21,101 @@ config ESPI_PERIPHERAL_HOST_IO
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config ESPI_PERIPHERAL_DEBUG_PORT_80
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default y
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config ESPI_PERIPHERAL_EC_HOST_CMD
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default y
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choice IT8XXX2_H2RAM_HC_SIZE_CHOICE
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prompt "H2RAM space for ec host command"
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default IT8XXX2_H2RAM_HC_SIZE_256
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depends on ESPI_PERIPHERAL_EC_HOST_CMD
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config IT8XXX2_H2RAM_HC_SIZE_16
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bool "16"
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config IT8XXX2_H2RAM_HC_SIZE_32
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bool "32"
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config IT8XXX2_H2RAM_HC_SIZE_64
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bool "64"
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config IT8XXX2_H2RAM_HC_SIZE_128
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bool "128"
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config IT8XXX2_H2RAM_HC_SIZE_256
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bool "256"
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config IT8XXX2_H2RAM_HC_SIZE_512
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bool "512"
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config IT8XXX2_H2RAM_HC_SIZE_1024
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bool "1024"
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config IT8XXX2_H2RAM_HC_SIZE_2048
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bool "2048"
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endchoice
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config ESPI_IT8XXX2_HC_H2RAM_SIZE
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int
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depends on ESPI_PERIPHERAL_EC_HOST_CMD
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default 16 if IT8XXX2_H2RAM_HC_SIZE_16
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default 32 if IT8XXX2_H2RAM_HC_SIZE_32
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default 64 if IT8XXX2_H2RAM_HC_SIZE_64
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default 128 if IT8XXX2_H2RAM_HC_SIZE_128
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default 256 if IT8XXX2_H2RAM_HC_SIZE_256
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default 512 if IT8XXX2_H2RAM_HC_SIZE_512
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default 1024 if IT8XXX2_H2RAM_HC_SIZE_1024
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default 2048 if IT8XXX2_H2RAM_HC_SIZE_2048
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config ESPI_PERIPHERAL_ACPI_SHM_REGION
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default y
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choice IT8XXX2_H2RAM_ACPI_SHM_SIZE_CHOICE
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prompt "H2RAM space for ACPI shared memory region"
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default IT8XXX2_H2RAM_ACPI_SHM_SIZE_256
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depends on ESPI_PERIPHERAL_ACPI_SHM_REGION
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_16
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bool "16"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_32
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bool "32"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_64
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bool "64"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_128
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bool "128"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_256
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bool "256"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_512
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bool "512"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_1024
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bool "1024"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_2048
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bool "2048"
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endchoice
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config ESPI_IT8XXX2_ACPI_SHM_H2RAM_SIZE
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int
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depends on ESPI_PERIPHERAL_ACPI_SHM_REGION
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default 16 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_16
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default 32 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_32
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default 64 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_64
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default 128 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_128
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default 256 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_256
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default 512 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_512
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default 1024 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_1024
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default 2048 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_2048
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config ESPI_PERIPHERAL_CUSTOM_OPCODE
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default y
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config ESPI_FLASH_CHANNEL
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default y
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@ -26,6 +26,7 @@ LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
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#define IT8XXX2_KBC_OBE_IRQ DT_INST_IRQ_BY_IDX(0, 3, irq)
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#define IT8XXX2_PMC1_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 4, irq)
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#define IT8XXX2_PORT_80_IRQ DT_INST_IRQ_BY_IDX(0, 5, irq)
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#define IT8XXX2_PMC2_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 6, irq)
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/* General Capabilities and Configuration 1 */
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#define IT8XXX2_ESPI_MAX_FREQ_MASK GENMASK(2, 0)
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@ -72,6 +73,7 @@ struct espi_it8xxx2_config {
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uintptr_t base_ec2i;
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uintptr_t base_kbc;
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uintptr_t base_pmc;
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uintptr_t base_smfi;
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};
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struct espi_it8xxx2_data {
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@ -153,6 +155,125 @@ static const struct ec2i_t pmc1_settings[] = {
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{HOST_INDEX_LDA, 0x01},
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};
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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#define IT8XXX2_ESPI_HC_DATA_PORT_MSB \
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((CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM >> 8) & 0xff)
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#define IT8XXX2_ESPI_HC_DATA_PORT_LSB \
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(CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM & 0xff)
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#define IT8XXX2_ESPI_HC_CMD_PORT_MSB \
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(((CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM + 4) >> 8) & 0xff)
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#define IT8XXX2_ESPI_HC_CMD_PORT_LSB \
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((CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM + 4) & 0xff)
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static const struct ec2i_t pmc2_settings[] = {
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/* Select logical device 12h(PM2 host command) */
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{HOST_INDEX_LDN, LDN_PMC2},
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/* I/O Port Base Address (data/command ports) */
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{HOST_INDEX_IOBAD0_MSB, IT8XXX2_ESPI_HC_DATA_PORT_MSB},
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{HOST_INDEX_IOBAD0_LSB, IT8XXX2_ESPI_HC_DATA_PORT_LSB},
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{HOST_INDEX_IOBAD1_MSB, IT8XXX2_ESPI_HC_CMD_PORT_MSB},
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{HOST_INDEX_IOBAD1_LSB, IT8XXX2_ESPI_HC_CMD_PORT_LSB},
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/* Set IRQ=00h for logical device */
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{HOST_INDEX_IRQNUMX, 0x00},
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/* Enable logical device */
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{HOST_INDEX_LDA, 0x01},
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};
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#endif
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#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \
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defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
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/*
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* Host to RAM (H2RAM) memory mapping.
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* This feature allows host access EC's memory directly by eSPI I/O cycles.
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* Mapping range is 4K bytes and base address is adjustable.
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* Eg. the I/O cycle 800h~8ffh from host can be mapped to x800h~x8ffh.
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* Linker script of h2ram.ld will make the pool 4K aligned.
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*/
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#define IT8XXX2_ESPI_H2RAM_POOL_SIZE 0x1000
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static uint8_t h2ram_pool[IT8XXX2_ESPI_H2RAM_POOL_SIZE]
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__attribute__((section(".h2ram_pool")));
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#if defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
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#define H2RAM_ACPI_SHM_MAX ((CONFIG_ESPI_IT8XXX2_ACPI_SHM_H2RAM_SIZE) + \
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(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM))
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#if (H2RAM_ACPI_SHM_MAX > IT8XXX2_ESPI_H2RAM_POOL_SIZE)
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#error "ACPI shared memory region out of h2ram"
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#endif
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#endif /* CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION */
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#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD)
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#define H2RAM_EC_HOST_CMD_MAX ((CONFIG_ESPI_IT8XXX2_HC_H2RAM_SIZE) + \
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(CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM))
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#if (H2RAM_EC_HOST_CMD_MAX > IT8XXX2_ESPI_H2RAM_POOL_SIZE)
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#error "EC host command parameters out of h2ram"
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#endif
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#endif /* CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD */
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#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) && \
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defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
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#if (MIN(H2RAM_ACPI_SHM_MAX, H2RAM_EC_HOST_CMD_MAX) > \
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MAX(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM, \
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CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM))
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#error "ACPI and HC sections of h2ram overlap"
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#endif
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#endif
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#define H2RAM_WINDOW_SIZE(ram_size) ((find_msb_set((ram_size) / 16) - 1) & 0x7)
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static const struct ec2i_t smfi_settings[] = {
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/* Select logical device 0Fh(SMFI) */
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{HOST_INDEX_LDN, LDN_SMFI},
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/* Internal RAM base address on eSPI I/O space */
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{HOST_INDEX_DSLDC6, 0x00},
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/* Enable H2RAM eSPI I/O cycle */
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{HOST_INDEX_DSLDC7, 0x01},
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/* Enable logical device */
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{HOST_INDEX_LDA, 0x01},
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};
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static void smfi_it8xxx2_init(const struct device *dev)
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{
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const struct espi_it8xxx2_config *const config = dev->config;
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struct flash_it8xxx2_regs *const smfi_reg =
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(struct flash_it8xxx2_regs *)config->base_smfi;
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struct gctrl_it8xxx2_regs *const gctrl = ESPI_IT8XXX2_GET_GCTRL_BASE;
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uint8_t h2ram_offset;
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/* Set the host to RAM cycle address offset */
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h2ram_offset = ((uint32_t)h2ram_pool & 0xffff) /
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IT8XXX2_ESPI_H2RAM_POOL_SIZE;
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gctrl->GCTRL_H2ROFSR |= h2ram_offset;
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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memset(&h2ram_pool[CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM], 0,
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CONFIG_ESPI_IT8XXX2_HC_H2RAM_SIZE);
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/* Set host RAM window 0 base address */
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smfi_reg->SMFI_HRAMW0BA =
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(CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM >> 4) & 0xff;
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/* Set host RAM window 0 size. (allow R/W) */
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smfi_reg->SMFI_HRAMW0AAS =
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H2RAM_WINDOW_SIZE(CONFIG_ESPI_IT8XXX2_HC_H2RAM_SIZE);
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/* Enable window 0, H2RAM through IO cycle */
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smfi_reg->SMFI_HRAMWC |= (SMFI_H2RAMPS | SMFI_H2RAMW0E);
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#endif
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#ifdef CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
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memset(&h2ram_pool[CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM], 0,
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CONFIG_ESPI_IT8XXX2_ACPI_SHM_H2RAM_SIZE);
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/* Set host RAM window 1 base address */
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smfi_reg->SMFI_HRAMW1BA =
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(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM >> 4) & 0xff;
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/* Set host RAM window 1 size. (read-only) */
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smfi_reg->SMFI_HRAMW1AAS =
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H2RAM_WINDOW_SIZE(CONFIG_ESPI_IT8XXX2_ACPI_SHM_H2RAM_SIZE) |
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SMFI_HRAMWXWPE_ALL;
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/* Enable window 1, H2RAM through IO cycle */
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smfi_reg->SMFI_HRAMWC |= (SMFI_H2RAMPS | SMFI_H2RAMW1E);
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#endif
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}
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#endif /* CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD ||
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* CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
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*/
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static void ec2i_it8xxx2_wait_status_cleared(const struct device *dev,
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uint8_t mask)
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{
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@ -230,6 +351,13 @@ static void pnpcfg_it8xxx2_init(const struct device *dev)
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if (IS_ENABLED(CONFIG_ESPI_PERIPHERAL_HOST_IO)) {
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PNPCFG(pmc1);
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}
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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PNPCFG(pmc2);
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#endif
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#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \
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defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
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PNPCFG(smfi);
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#endif
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}
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/* KBC (port 60h/64h) */
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@ -387,6 +515,41 @@ static void port80_it8xxx2_init(const struct device *dev)
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}
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#endif
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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/* PMC 2 (Host command port CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM) */
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static void pmc2_it8xxx2_ibf_isr(const struct device *dev)
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{
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const struct espi_it8xxx2_config *const config = dev->config;
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struct espi_it8xxx2_data *const data = dev->data;
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struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
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struct espi_event evt = {
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ESPI_BUS_PERIPHERAL_NOTIFICATION,
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ESPI_PERIPHERAL_EC_HOST_CMD,
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ESPI_PERIPHERAL_NODATA
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};
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/* Set processing flag before reading command byte */
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pmc_reg->PM2STS |= PMC_PM2STS_GPF;
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evt.evt_data = pmc_reg->PM2DI;
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espi_send_callbacks(&data->callbacks, dev, evt);
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}
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static void pmc2_it8xxx2_init(const struct device *dev)
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{
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const struct espi_it8xxx2_config *const config = dev->config;
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struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
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/* Dedicated interrupt for PMC2 */
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pmc_reg->MBXCTRL |= PMC_MBXCTRL_DINT;
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/* Enable pmc2 input buffer full interrupt */
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pmc_reg->PM2CTL |= PMC_PM2CTL_IBFIE;
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IRQ_CONNECT(IT8XXX2_PMC2_IBF_IRQ, 0, pmc2_it8xxx2_ibf_isr,
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DEVICE_DT_INST_GET(0), 0);
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irq_enable(IT8XXX2_PMC2_IBF_IRQ);
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}
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#endif
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/* eSPI api functions */
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#define VW_CHAN(signal, index, level, valid) \
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[signal] = {.vw_index = index, .level_mask = level, .valid_mask = valid}
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@ -616,10 +779,30 @@ static int espi_it8xxx2_read_lpc_request(const struct device *dev,
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case EACPI_READ_STS:
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*data = pmc_reg->PM1STS;
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break;
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#ifdef CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
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case EACPI_GET_SHARED_MEMORY:
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*data = (uint32_t)&h2ram_pool[
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CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM];
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break;
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#endif /* CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION */
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default:
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return -EINVAL;
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}
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} else {
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}
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#ifdef CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
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else if (op >= ECUSTOM_START_OPCODE && op <= ECUSTOM_MAX_OPCODE) {
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switch (op) {
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case ECUSTOM_HOST_CMD_GET_PARAM_MEMORY:
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*data = (uint32_t)&h2ram_pool[
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CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM];
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break;
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default:
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return -EINVAL;
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}
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}
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#endif /* CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE */
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else {
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return -ENOTSUP;
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}
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@ -695,7 +878,33 @@ static int espi_it8xxx2_write_lpc_request(const struct device *dev,
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default:
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return -EINVAL;
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}
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} else {
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}
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#ifdef CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
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else if (op >= ECUSTOM_START_OPCODE && op <= ECUSTOM_MAX_OPCODE) {
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struct pmc_regs *const pmc_reg =
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(struct pmc_regs *)config->base_pmc;
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switch (op) {
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/* Enable/Disable PMC1 (port 62h/66h) interrupt */
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case ECUSTOM_HOST_SUBS_INTERRUPT_EN:
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if (*data) {
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pmc_reg->PM1CTL |= PMC_PM1CTL_IBFIE;
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} else {
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pmc_reg->PM1CTL &= ~PMC_PM1CTL_IBFIE;
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}
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break;
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case ECUSTOM_HOST_CMD_SEND_RESULT:
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/* Write result to data output port (set OBF status) */
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pmc_reg->PM2DO = (*data & 0xff);
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/* Clear processing flag */
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pmc_reg->PM2STS &= ~PMC_PM2STS_GPF;
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break;
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default:
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return -EINVAL;
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}
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}
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#endif /* CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE */
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else {
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return -ENOTSUP;
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}
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@ -1606,6 +1815,7 @@ static const struct espi_it8xxx2_config espi_it8xxx2_config_0 = {
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.base_ec2i = DT_INST_REG_ADDR_BY_IDX(0, 4),
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.base_kbc = DT_INST_REG_ADDR_BY_IDX(0, 5),
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.base_pmc = DT_INST_REG_ADDR_BY_IDX(0, 6),
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.base_smfi = DT_INST_REG_ADDR_BY_IDX(0, 7),
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};
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DEVICE_DT_INST_DEFINE(0, &espi_it8xxx2_init, NULL,
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@ -1642,6 +1852,14 @@ static int espi_it8xxx2_init(const struct device *dev)
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/* Accept Port 80h Cycle */
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port80_it8xxx2_init(dev);
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#endif
|
||||
#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \
|
||||
defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
|
||||
smfi_it8xxx2_init(dev);
|
||||
#endif
|
||||
#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
|
||||
/* enable pmc2 for host command port */
|
||||
pmc2_it8xxx2_init(dev);
|
||||
#endif
|
||||
|
||||
/* Reset vwidx_cached_flag[] at initialization */
|
||||
espi_it8xxx2_reset_vwidx_cache(dev);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue