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boards/up_squared: temporarily remove I2C support

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This needs to be pushed down to the SoC level, as it's an Apollo Lake
feature, not a feature of the UpSquared. Remove the Apollo Lake
references to the PCI devices because these will not be used when I2C
support is restored.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This commit is contained in:
Charles E. Youse 2019-05-15 20:34:26 -07:00 • committed by Anas Nashif
commit 35d0ae39d8
5 changed files with 0 additions and 282 deletions
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108
boards/x86/up_squared/up_squared.dts
View file

@ -12,8 +12,6 @@
#define DT_SRAM_SIZE DT_SIZE_M(2048)
#include <apollo_lake.dtsi>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pcie/pcie.h>
/ {
model = "up_squared";
@ -28,112 +26,6 @@
zephyr,uart-pipe = &uart1;
zephyr,bt-mon-uart = &uart1;
};
soc {
i2c0: i2c@91534000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x91534000 0x1000>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_0";
status = "ok";
};
i2c1: i2c@91532000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x91532000 0x1000>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_1";
status = "ok";
};
i2c2: i2c@91530000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x91530000 0x1000>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_2";
status = "ok";
};
i2c3: i2c@9152e000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x9152e000 0x1000>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_3";
status = "ok";
};
i2c4: i2c@9152c000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x9152c000 0x1000>;
interrupts = <31 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_4";
status = "ok";
};
i2c5: i2c@9152a000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x9152a000 0x1000>;
interrupts = <32 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_5";
status = "ok";
};
i2c6: i2c@91528000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x91528000 0x1000>;
interrupts = <33 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_6";
status = "ok";
};
i2c7: i2c@91526000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x91526000 0x1000>;
interrupts = <34 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_7";
status = "ok";
};
};
};
&uart0 {

1
boards/x86/up_squared/up_squared_defconfig
View file

@ -11,4 +11,3 @@ CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_CONSOLE=y
CONFIG_I2C=y

107
boards/x86/up_squared/up_squared_sbl.dts
View file

@ -12,7 +12,6 @@
#define DT_SRAM_SIZE DT_SIZE_M(2048)
#include <apollo_lake.dtsi>
#include <dt-bindings/i2c/i2c.h>
/ {
model = "up_squared";
@ -27,112 +26,6 @@
zephyr,uart-pipe = &uart1;
zephyr,bt-mon-uart = &uart1;
};
soc {
i2c0: i2c@81444000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x81444000 0x1000>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_0";
status = "ok";
};
i2c1: i2c@81442000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x81442000 0x1000>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_1";
status = "ok";
};
i2c2: i2c@81440000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x81440000 0x1000>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_2";
status = "ok";
};
i2c3: i2c@8143e000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x8143e000 0x1000>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_3";
status = "ok";
};
i2c4: i2c@8143c000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x8143c000 0x1000>;
interrupts = <31 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_4";
status = "ok";
};
i2c5: i2c@8143a000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x8143a000 0x1000>;
interrupts = <32 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_5";
status = "ok";
};
i2c6: i2c@81438000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x81438000 0x1000>;
interrupts = <33 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_6";
status = "ok";
};
i2c7: i2c@81436000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x81436000 0x1000>;
interrupts = <34 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_7";
status = "ok";
};
};
};
&uart0 {

1
boards/x86/up_squared/up_squared_sbl_defconfig
View file

@ -11,4 +11,3 @@ CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_CONSOLE=y
CONFIG_I2C=y

65
soc/x86/apollo_lake/soc.h
View file

@ -45,71 +45,6 @@
*/
#define pci_pin2irq(bus, dev, pin) (pin)
/* I2C controllers */
#define I2C_DW_0_PCI_VENDOR_ID 0x8086
#define I2C_DW_0_PCI_DEVICE_ID 0x5aac
#define I2C_DW_0_PCI_CLASS 0x11
#define I2C_DW_0_PCI_BUS 0
#define I2C_DW_0_PCI_DEV 16
#define I2C_DW_0_PCI_FUNCTION 0
#define I2C_DW_0_PCI_BAR 0
#define I2C_DW_1_PCI_VENDOR_ID 0x8086
#define I2C_DW_1_PCI_DEVICE_ID 0x5aae
#define I2C_DW_1_PCI_CLASS 0x11
#define I2C_DW_1_PCI_BUS 0
#define I2C_DW_1_PCI_DEV 16
#define I2C_DW_1_PCI_FUNCTION 1
#define I2C_DW_1_PCI_BAR 0
#define I2C_DW_2_PCI_VENDOR_ID 0x8086
#define I2C_DW_2_PCI_DEVICE_ID 0x5ab0
#define I2C_DW_2_PCI_CLASS 0x11
#define I2C_DW_2_PCI_BUS 0
#define I2C_DW_2_PCI_DEV 16
#define I2C_DW_2_PCI_FUNCTION 2
#define I2C_DW_2_PCI_BAR 0
#define I2C_DW_3_PCI_VENDOR_ID 0x8086
#define I2C_DW_3_PCI_DEVICE_ID 0x5ab2
#define I2C_DW_3_PCI_CLASS 0x11
#define I2C_DW_3_PCI_BUS 0
#define I2C_DW_3_PCI_DEV 16
#define I2C_DW_3_PCI_FUNCTION 3
#define I2C_DW_3_PCI_BAR 0
#define I2C_DW_4_PCI_VENDOR_ID 0x8086
#define I2C_DW_4_PCI_DEVICE_ID 0x5ab4
#define I2C_DW_4_PCI_CLASS 0x11
#define I2C_DW_4_PCI_BUS 0
#define I2C_DW_4_PCI_DEV 17
#define I2C_DW_4_PCI_FUNCTION 0
#define I2C_DW_4_PCI_BAR 0
#define I2C_DW_5_PCI_VENDOR_ID 0x8086
#define I2C_DW_5_PCI_DEVICE_ID 0x5ab6
#define I2C_DW_5_PCI_CLASS 0x11
#define I2C_DW_5_PCI_BUS 0
#define I2C_DW_5_PCI_DEV 17
#define I2C_DW_5_PCI_FUNCTION 1
#define I2C_DW_5_PCI_BAR 0
#define I2C_DW_6_PCI_VENDOR_ID 0x8086
#define I2C_DW_6_PCI_DEVICE_ID 0x5ab8
#define I2C_DW_6_PCI_CLASS 0x11
#define I2C_DW_6_PCI_BUS 0
#define I2C_DW_6_PCI_DEV 17
#define I2C_DW_6_PCI_FUNCTION 2
#define I2C_DW_6_PCI_BAR 0
#define I2C_DW_7_PCI_VENDOR_ID 0x8086
#define I2C_DW_7_PCI_DEVICE_ID 0x5aba
#define I2C_DW_7_PCI_CLASS 0x11
#define I2C_DW_7_PCI_BUS 0
#define I2C_DW_7_PCI_DEV 17
#define I2C_DW_7_PCI_FUNCTION 3
#define I2C_DW_7_PCI_BAR 0
#endif /* CONFIG_PCI */
#endif /* __SOC_H_ */