soc: renesas: add support for RA8T1 SoC
Initial commit to support RA8T1 SoC Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com> Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
This commit is contained in:
Duy Phuong Hoang. Nguyen
Fabio Baltieri
parent
f75c7ae24c
commit
356d331db5
10 changed files with 428 additions and 0 deletions
18
dts/arm/renesas/ra/ra8/r7fa8t1ahecbd.dtsi
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18
dts/arm/renesas/ra/ra8/r7fa8t1ahecbd.dtsi
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@ -0,0 +1,18 @@
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra8/r7fa8t1xh.dtsi>
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/ {
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soc {
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flash-controller@407fe000 {
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flash0: flash@2000000 {
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compatible = "soc-nv-flash";
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reg = <0x02000000 DT_SIZE_M(2)>;
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};
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};
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};
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};
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208
dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
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208
dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
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@ -0,0 +1,208 @@
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra8/ra8x1.dtsi>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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/ {
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clocks: clocks {
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xtal: clock-xtal {
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compatible = "renesas,ra8-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(24)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra8-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pll: pll {
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compatible = "renesas,ra8-cgc-pll";
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#clock-cells = <0>;
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/* PLL */
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source = <RA_PLL_SOURCE_MAIN_OSC>;
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div = <RA_PLL_DIV_2>;
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mul = <80 0>;
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divp = <RA_PLL_DIV_2>;
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freqp = <DT_FREQ_M(480)>;
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divq = <RA_PLL_DIV_2>;
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freqq = <DT_FREQ_M(480)>;
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divr = <RA_PLL_DIV_2>;
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freqr = <DT_FREQ_M(480)>;
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status = "disabled";
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};
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pll2: pll2 {
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compatible = "renesas,ra8-cgc-pll";
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#clock-cells = <0>;
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/* PLL2 */
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source = <RA_PLL_SOURCE_DISABLE>;
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div = <RA_PLL_DIV_2>;
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mul = <96 0>;
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divp = <RA_PLL_DIV_2>;
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freqp = <DT_FREQ_M(0)>;
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divq = <RA_PLL_DIV_2>;
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freqq = <DT_FREQ_M(0)>;
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divr = <RA_PLL_DIV_2>;
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freqr = <DT_FREQ_M(0)>;
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status = "disabled";
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};
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pclkblock: pclkblock {
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compatible = "renesas,ra8-cgc-pclk-block";
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#clock-cells = <0>;
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sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
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status = "okay";
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cpuclk: cpuclk {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_1>;
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#clock-cells = <2>;
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status = "okay";
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};
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iclk: iclk {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclka: pclka {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_8>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkc: pclkc {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_8>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclke: pclke {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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bclk: bclk {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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bclkout: bclkout {
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compatible = "renesas,ra8-cgc-busclk";
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clk_out_div = <2>;
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sdclk = <1>;
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#clock-cells = <0>;
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};
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#clock-cells = <2>;
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status = "okay";
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};
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fclk: fclk {
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compatible = "renesas,ra8-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_8>;
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#clock-cells = <2>;
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status = "okay";
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};
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clkout: clkout {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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sciclk: sciclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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spiclk: spiclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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canfdclk: canfdclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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i3cclk: i3cclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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uclk: uclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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u60clk: u60clk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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octaspiclk: octaspiclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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lcdclk: lcdclk {
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compatible = "renesas,ra8-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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};
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};
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};
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12
soc/renesas/ra/ra8t1/CMakeLists.txt
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12
soc/renesas/ra/ra8t1/CMakeLists.txt
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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15
soc/renesas/ra/ra8t1/Kconfig
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15
soc/renesas/ra/ra8t1/Kconfig
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA8T1
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select ARM
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select CPU_CORTEX_M85
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select CPU_HAS_ARM_SAU
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select ARMV8_M_DSP
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select FPU
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select HAS_SWO
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select XIP
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select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
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select HAS_RENESAS_RA_FSP
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12
soc/renesas/ra/ra8t1/Kconfig.defconfig
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12
soc/renesas/ra/ra8t1/Kconfig.defconfig
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RA8T1
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config NUM_IRQS
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default 96
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config PINCTRL
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default y
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endif # SOC_SERIES_RA8T1
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21
soc/renesas/ra/ra8t1/Kconfig.soc
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21
soc/renesas/ra/ra8t1/Kconfig.soc
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA8T1
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bool
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select SOC_FAMILY_RENESAS_RA
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help
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Renesas RA8T1 series
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config SOC_SERIES
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default "ra8t1" if SOC_SERIES_RA8T1
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config SOC_R7FA8T1AHECBD
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bool
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select SOC_SERIES_RA8T1
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help
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R7FA8T1AHECBD
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config SOC
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default "r7fa8t1ahecbd" if SOC_R7FA8T1AHECBD
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79
soc/renesas/ra/ra8t1/sections.ld
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79
soc/renesas/ra/ra8t1/sections.ld
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.code_in_ram :
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{
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. = ALIGN(4);
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__Code_In_RAM_Start = .;
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KEEP(*(.code_in_ram*))
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__Code_In_RAM_End = .;
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} > RAMABLE_REGION
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SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
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{
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/* If DTC is used, put the DTC vector table at the start of SRAM.
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This avoids memory holes due to 1K alignment required by it. */
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*(.fsp_dtc_vector_table)
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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SECTION_PROLOGUE(.option_setting_ofs,,)
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{
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__OPTION_SETTING_OFS_Start = .;
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KEEP(*(.option_setting_ofs0))
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. = __OPTION_SETTING_OFS_Start + 0x04;
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KEEP(*(.option_setting_ofs2))
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. = __OPTION_SETTING_OFS_Start + 0x10;
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KEEP(*(.option_setting_dualsel))
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__OPTION_SETTING_OFS_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
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SECTION_PROLOGUE(.option_setting_sas,,)
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{
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__OPTION_SETTING_SAS_Start = .;
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KEEP(*(.option_setting_sas))
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__OPTION_SETTING_SAS_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
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SECTION_PROLOGUE(.option_setting_s,,)
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{
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__OPTION_SETTING_S_Start = .;
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KEEP(*(.option_setting_ofs1_sec))
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. = __OPTION_SETTING_S_Start + 0x04;
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KEEP(*(.option_setting_ofs3_sec))
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. = __OPTION_SETTING_S_Start + 0x10;
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KEEP(*(.option_setting_banksel_sec))
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. = __OPTION_SETTING_S_Start + 0x40;
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KEEP(*(.option_setting_bps_sec0))
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. = __OPTION_SETTING_S_Start + 0x44;
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KEEP(*(.option_setting_bps_sec1))
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. = __OPTION_SETTING_S_Start + 0x48;
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KEEP(*(.option_setting_bps_sec2))
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. = __OPTION_SETTING_S_Start + 0x4C;
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KEEP(*(.option_setting_bps_sec3))
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. = __OPTION_SETTING_S_Start + 0x60;
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KEEP(*(.option_setting_pbps_sec0))
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. = __OPTION_SETTING_S_Start + 0x64;
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KEEP(*(.option_setting_pbps_sec1))
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. = __OPTION_SETTING_S_Start + 0x68;
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KEEP(*(.option_setting_pbps_sec2))
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. = __OPTION_SETTING_S_Start + 0x6C;
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KEEP(*(.option_setting_pbps_sec3))
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. = __OPTION_SETTING_S_Start + 0x80;
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KEEP(*(.option_setting_ofs1_sel))
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. = __OPTION_SETTING_S_Start + 0x84;
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KEEP(*(.option_setting_ofs3_sel))
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. = __OPTION_SETTING_S_Start + 0x90;
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KEEP(*(.option_setting_banksel_sel))
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. = __OPTION_SETTING_S_Start + 0xC0;
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KEEP(*(.option_setting_bps_sel0))
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. = __OPTION_SETTING_S_Start + 0xC4;
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KEEP(*(.option_setting_bps_sel1))
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. = __OPTION_SETTING_S_Start + 0xC8;
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KEEP(*(.option_setting_bps_sel2))
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. = __OPTION_SETTING_S_Start + 0xCC;
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KEEP(*(.option_setting_bps_sel3))
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__OPTION_SETTING_S_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
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44
soc/renesas/ra/ra8t1/soc.c
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44
soc/renesas/ra/ra8t1/soc.c
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for Renesas RA8T1 family processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <cmsis_core.h>
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#include <zephyr/arch/arm/nmi.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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#include <bsp_api.h>
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uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
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volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int renesas_ra8t1_init(void)
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{
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SystemCoreClock = BSP_MOCO_HZ;
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g_protect_pfswe_counter = 0;
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return 0;
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}
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SYS_INIT(renesas_ra8t1_init, PRE_KERNEL_1, 0);
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16
soc/renesas/ra/ra8t1/soc.h
Normal file
16
soc/renesas/ra/ra8t1/soc.h
Normal file
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the Renesas RA8T1 family MCU
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RA8T1_SOC_H_
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#define ZEPHYR_SOC_RENESAS_RA8T1_SOC_H_
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#include <bsp_api.h>
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#endif /* ZEPHYR_SOC_RENESAS_RA8T1_SOC_H_ */
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@ -10,3 +10,6 @@ family:
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- name: ra8d1
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socs:
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- name: r7fa8d1bhecbd
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- name: ra8t1
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socs:
|
||||
- name: r7fa8t1ahecbd
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue