soc: renesas: add support for RA8T1 SoC

Initial commit to support RA8T1 SoC

Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>

dts/arm/renesas/ra/ra8/r7fa8t1ahecbd.dtsi

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra8/r7fa8t1xh.dtsi>
+
+/ {
+	soc {
+		flash-controller@407fe000 {
+			flash0: flash@2000000 {
+				compatible = "soc-nv-flash";
+				reg = <0x02000000 DT_SIZE_M(2)>;
+			};
+		};
+	};
+};

dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi

@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra8/ra8x1.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/ {
+	clocks: clocks {
+		xtal: clock-xtal {
+			compatible = "renesas,ra8-cgc-external-clock";
+			clock-frequency = <DT_FREQ_M(24)>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		hoco: clock-hoco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(48)>;
+			#clock-cells = <0>;
+		};
+
+		moco: clock-moco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+		};
+
+		loco: clock-loco {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		subclk: clock-subclk {
+			compatible = "renesas,ra8-cgc-subclk";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			compatible = "renesas,ra8-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL */
+			source = <RA_PLL_SOURCE_MAIN_OSC>;
+			div = <RA_PLL_DIV_2>;
+			mul = <80 0>;
+			divp = <RA_PLL_DIV_2>;
+			freqp = <DT_FREQ_M(480)>;
+			divq = <RA_PLL_DIV_2>;
+			freqq = <DT_FREQ_M(480)>;
+			divr = <RA_PLL_DIV_2>;
+			freqr = <DT_FREQ_M(480)>;
+			status = "disabled";
+		};
+
+		pll2: pll2 {
+			compatible = "renesas,ra8-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL2 */
+			source = <RA_PLL_SOURCE_DISABLE>;
+			div = <RA_PLL_DIV_2>;
+			mul = <96 0>;
+			divp = <RA_PLL_DIV_2>;
+			freqp = <DT_FREQ_M(0)>;
+			divq = <RA_PLL_DIV_2>;
+			freqq = <DT_FREQ_M(0)>;
+			divr = <RA_PLL_DIV_2>;
+			freqr = <DT_FREQ_M(0)>;
+			status = "disabled";
+		};
+
+		pclkblock: pclkblock {
+			compatible = "renesas,ra8-cgc-pclk-block";
+			#clock-cells = <0>;
+			sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
+			status = "okay";
+
+			cpuclk: cpuclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			iclk: iclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclka: pclka {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkb: pclkb {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_8>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkc: pclkc {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_8>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkd: pclkd {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclke: pclke {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			bclk: bclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				bclkout: bclkout {
+					compatible = "renesas,ra8-cgc-busclk";
+					clk_out_div = <2>;
+					sdclk = <1>;
+					#clock-cells = <0>;
+				};
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			fclk: fclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_8>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			clkout: clkout {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			sciclk: sciclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			spiclk: spiclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			canfdclk: canfdclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			i3cclk: i3cclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			uclk: uclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			u60clk: u60clk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			octaspiclk: octaspiclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			lcdclk: lcdclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+		};
+	};
+};

soc/renesas/ra/ra8t1/CMakeLists.txt

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/ra/ra8t1/Kconfig

@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA8T1
+	select ARM
+	select CPU_CORTEX_M85
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_SAU
+	select ARMV8_M_DSP
+	select FPU
+	select HAS_SWO
+	select XIP
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+	select HAS_RENESAS_RA_FSP

soc/renesas/ra/ra8t1/Kconfig.defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA8T1
+
+config NUM_IRQS
+	default 96
+
+config PINCTRL
+	default y
+
+endif # SOC_SERIES_RA8T1

soc/renesas/ra/ra8t1/Kconfig.soc

@@ -0,0 +1,21 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+
+config SOC_SERIES_RA8T1
+	bool
+	select SOC_FAMILY_RENESAS_RA
+	help
+		Renesas RA8T1 series
+
+config SOC_SERIES
+	default "ra8t1" if SOC_SERIES_RA8T1
+
+config SOC_R7FA8T1AHECBD
+	bool
+	select SOC_SERIES_RA8T1
+	help
+		R7FA8T1AHECBD
+
+config SOC
+	default "r7fa8t1ahecbd" if SOC_R7FA8T1AHECBD

soc/renesas/ra/ra8t1/sections.ld

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+	. = ALIGN(4);
+	__Code_In_RAM_Start = .;
+	KEEP(*(.code_in_ram*))
+	__Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+	/* If DTC is used, put the DTC vector table at the start of SRAM.
+		This avoids memory holes due to 1K alignment required by it. */
+	*(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+	__OPTION_SETTING_OFS_Start = .;
+	KEEP(*(.option_setting_ofs0))
+	. = __OPTION_SETTING_OFS_Start + 0x04;
+	KEEP(*(.option_setting_ofs2))
+	. = __OPTION_SETTING_OFS_Start + 0x10;
+	KEEP(*(.option_setting_dualsel))
+	__OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+	__OPTION_SETTING_SAS_Start = .;
+	KEEP(*(.option_setting_sas))
+	__OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+	__OPTION_SETTING_S_Start = .;
+	KEEP(*(.option_setting_ofs1_sec))
+	. = __OPTION_SETTING_S_Start + 0x04;
+	KEEP(*(.option_setting_ofs3_sec))
+	. = __OPTION_SETTING_S_Start + 0x10;
+	KEEP(*(.option_setting_banksel_sec))
+	. = __OPTION_SETTING_S_Start + 0x40;
+	KEEP(*(.option_setting_bps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x44;
+	KEEP(*(.option_setting_bps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x48;
+	KEEP(*(.option_setting_bps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x4C;
+	KEEP(*(.option_setting_bps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x60;
+	KEEP(*(.option_setting_pbps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x64;
+	KEEP(*(.option_setting_pbps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x68;
+	KEEP(*(.option_setting_pbps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x6C;
+	KEEP(*(.option_setting_pbps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x80;
+	KEEP(*(.option_setting_ofs1_sel))
+	. = __OPTION_SETTING_S_Start + 0x84;
+	KEEP(*(.option_setting_ofs3_sel))
+	. = __OPTION_SETTING_S_Start + 0x90;
+	KEEP(*(.option_setting_banksel_sel))
+	. = __OPTION_SETTING_S_Start + 0xC0;
+	KEEP(*(.option_setting_bps_sel0))
+	. = __OPTION_SETTING_S_Start + 0xC4;
+	KEEP(*(.option_setting_bps_sel1))
+	. = __OPTION_SETTING_S_Start + 0xC8;
+	KEEP(*(.option_setting_bps_sel2))
+	. = __OPTION_SETTING_S_Start + 0xCC;
+	KEEP(*(.option_setting_bps_sel3))
+	__OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF

soc/renesas/ra/ra8t1/soc.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA8T1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/arch/arm/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra8t1_init(void)
+{
+	SystemCoreClock = BSP_MOCO_HZ;
+	g_protect_pfswe_counter = 0;
+
+	return 0;
+}
+
+SYS_INIT(renesas_ra8t1_init, PRE_KERNEL_1, 0);

soc/renesas/ra/ra8t1/soc.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA8T1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA8T1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA8T1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA8T1_SOC_H_ */

soc/renesas/ra/soc.yml

@@ -10,3 +10,6 @@ family:
       - name: ra8d1
         socs:
           - name: r7fa8d1bhecbd
+      - name: ra8t1
+        socs:
+          - name: r7fa8t1ahecbd