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drivers/spi/spi_intel.c: remove Quark SPI support

Browse source 
This was only used on Quark SoCs. It is no longer used, can no
longer be tested, and it's reliant upon the deprecated legacy PCI
subsystem. Remove it to prevent bitrot.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This commit is contained in:
Charles E. Youse 2019-08-23 08:56:22 -07:00 • committed by Anas Nashif
commit 34ffdd0aab
5 changed files with 0 additions and 680 deletions
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1
drivers/spi/CMakeLists.txt
View file

@ -4,7 +4,6 @@ zephyr_library()
zephyr_library_sources_ifdef(CONFIG_SPI_CC13XX_CC26XX spi_cc13xx_cc26xx.c)
zephyr_library_sources_ifdef(CONFIG_SPI_DW spi_dw.c)
zephyr_library_sources_ifdef(CONFIG_SPI_INTEL spi_intel.c)
zephyr_library_sources_ifdef(CONFIG_SPI_STM32 spi_ll_stm32.c)
zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_DSPI spi_mcux_dspi.c)
zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI spi_mcux_lpspi.c)

8
drivers/spi/Kconfig
View file

@ -180,14 +180,6 @@ config SPI_6_OP_MODES
endif # SPI_6
config SPI_INTEL
bool "Intel SPI controller driver"
depends on CPU_MINUTEIA
help
Enable support for Intel's SPI controllers. Such controller
was formerly found on XScale chips. It can be found nowadays
on CEXXXX Intel media controller and Quark CPU (2 of them).
source "drivers/spi/Kconfig.stm32"
source "drivers/spi/Kconfig.dw"

489
drivers/spi/spi_intel.c
View file

@ -1,489 +0,0 @@
/* spi_intel.c - Driver implementation for Intel SPI controller */
/*
* Copyright (c) 2015 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_DOMAIN "SPI Intel"
#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(spi_intel);
#include <errno.h>
#include <kernel.h>
#include <arch/cpu.h>
#include <sys/__assert.h>
#include <soc.h>
#include <init.h>
#include <sys/sys_io.h>
#include <power/power.h>
#include <drivers/spi.h>
#include "spi_intel.h"
#ifdef CONFIG_IOAPIC
#include <drivers/interrupt_controller/ioapic.h>
#endif
static void completed(struct device *dev, u32_t error)
{
struct spi_intel_data *spi = dev->driver_data;
if (error) {
goto out;
}
if (spi_context_tx_on(&spi->ctx) ||
spi_context_rx_on(&spi->ctx)) {
return;
}
out:
write_sscr1(spi->sscr1, spi->regs);
clear_bit_sscr0_sse(spi->regs);
spi_context_cs_control(&spi->ctx, false);
LOG_DBG("SPI transaction completed %s error",
error ? "with" : "without");
spi_context_complete(&spi->ctx, error ? -EIO : 0);
}
static void pull_data(struct device *dev)
{
struct spi_intel_data *spi = dev->driver_data;
while (read_sssr(spi->regs) & INTEL_SPI_SSSR_RNE) {
u32_t data = read_ssdr(spi->regs);
if (spi_context_rx_buf_on(&spi->ctx)) {
switch (spi->dfs) {
case 1:
UNALIGNED_PUT(data, (u8_t *)spi->ctx.rx_buf);
break;
case 2:
UNALIGNED_PUT(data, (u16_t *)spi->ctx.rx_buf);
break;
case 4:
UNALIGNED_PUT(data, (u32_t *)spi->ctx.rx_buf);
break;
}
spi_context_update_rx(&spi->ctx, spi->dfs, 1);
}
}
}
static void push_data(struct device *dev)
{
struct spi_intel_data *spi = dev->driver_data;
u32_t status;
while ((status = read_sssr(spi->regs)) & INTEL_SPI_SSSR_TNF) {
u32_t data = 0U;
if (status & INTEL_SPI_SSSR_RFS) {
break;
}
if (spi_context_tx_buf_on(&spi->ctx)) {
switch (spi->dfs) {
case 1:
data = UNALIGNED_GET((u8_t *)
(spi->ctx.tx_buf));
break;
case 2:
data = UNALIGNED_GET((u16_t *)
(spi->ctx.tx_buf));
break;
case 4:
data = UNALIGNED_GET((u32_t *)
(spi->ctx.tx_buf));
break;
}
}
write_ssdr(data, spi->regs);
spi_context_update_tx(&spi->ctx, spi->dfs, 1);
}
if (!spi_context_tx_on(&spi->ctx)) {
clear_bit_sscr1_tie(spi->regs);
}
}
static int spi_intel_configure(struct device *dev,
const struct spi_config *config)
{
struct spi_intel_data *spi = dev->driver_data;
LOG_DBG("%p (0x%x), %p", dev, spi->regs, config);
if (spi_context_configured(&spi->ctx, config)) {
/* Nothing to do */
return 0;
}
if (config->operation & (SPI_OP_MODE_SLAVE || SPI_TRANSFER_LSB
|| SPI_LINES_DUAL || SPI_LINES_QUAD ||
SPI_LINES_OCTAL)) {
return -EINVAL;
}
/* Determine how many bytes are required per-frame */
spi->dfs = SPI_WS_TO_DFS(SPI_WORD_SIZE_GET(config->operation));
/* Pre-configuring the registers to a clean state*/
write_sscr0(0, spi->regs);
write_sscr1(0, spi->regs);
/* Word size and clock rate */
spi->sscr0 = INTEL_SPI_SSCR0_DSS(SPI_WORD_SIZE_GET(config->operation)) |
INTEL_SPI_SSCR0_SCR(config->operation);
/* Tx/Rx thresholds
* Note: Rx thresholds needs to be 1, it does not seem to be able
* to trigger reliably any interrupt with another value though the
* rx fifo would be full
*/
spi->sscr1 = INTEL_SPI_SSCR1_TFT(INTEL_SPI_SSCR1_TFT_DFLT) |
INTEL_SPI_SSCR1_RFT(INTEL_SPI_SSCR1_RFT_DFLT);
/* SPI mode */
if (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) {
spi->sscr1 |= INTEL_SPI_SSCR1_SPO;
}
if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) {
spi->sscr1 |= INTEL_SPI_SSCR1_SPH;
}
if (SPI_MODE_GET(config->operation) & SPI_MODE_LOOP) {
spi->sscr1 |= INTEL_SPI_SSCR1_LBM;
}
/* Configuring the rate */
write_dds_rate(INTEL_SPI_DSS_RATE(config->frequency), spi->regs);
spi_context_cs_configure(&spi->ctx);
return 0;
}
static int transceive(struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs,
bool asynchronous,
struct k_poll_signal *signal)
{
struct spi_intel_data *spi = dev->driver_data;
int ret;
/* Check status */
if (test_bit_sscr0_sse(spi->regs) && test_bit_sssr_bsy(spi->regs)) {
LOG_DBG("Controller is busy");
return -EBUSY;
}
spi_context_lock(&spi->ctx, asynchronous, signal);
ret = spi_intel_configure(dev, config);
if (ret) {
goto out;
}
/* Set buffers info */
spi_context_buffers_setup(&spi->ctx, tx_bufs, rx_bufs, spi->dfs);
spi_context_cs_control(&spi->ctx, true);
/* Installing and Enabling the controller */
write_sscr0(spi->sscr0 | INTEL_SPI_SSCR0_SSE, spi->regs);
write_sscr1(spi->sscr1 | INTEL_SPI_SSCR1_RIE | INTEL_SPI_SSCR1_TIE,
spi->regs);
ret = spi_context_wait_for_completion(&spi->ctx);
out:
spi_context_release(&spi->ctx, ret);
return ret;
}
static int spi_intel_transceive(struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs)
{
LOG_DBG("%p, %p, %p", dev, tx_bufs, rx_bufs);
return transceive(dev, config, tx_bufs, rx_bufs, false, NULL);
}
#ifdef CONFIG_SPI_ASYNC
static int spi_intel_transceive_async(struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs,
struct k_poll_signal *async)
{
LOG_DBG("%p, %p, %p, %p", dev, tx_bufs, rx_bufs, async);
return transceive(dev, config, tx_bufs, rx_bufs, true, async);
}
#endif /* CONFIG_SPI_ASYNC */
static int spi_intel_release(struct device *dev,
const struct spi_config *config)
{
struct spi_intel_data *spi = dev->driver_data;
if (test_bit_sscr0_sse(spi->regs) && test_bit_sssr_bsy(spi->regs)) {
LOG_DBG("Controller is busy");
return -EBUSY;
}
spi_context_unlock_unconditionally(&spi->ctx);
return 0;
}
void spi_intel_isr(struct device *dev)
{
struct spi_intel_data *spi = dev->driver_data;
u32_t error = 0U;
u32_t status;
LOG_DBG("%p", dev);
status = read_sssr(spi->regs);
if (status & INTEL_SPI_SSSR_ROR) {
/* Unrecoverable error, ack it */
clear_bit_sssr_ror(spi->regs);
error = 1U;
goto out;
}
if (status & INTEL_SPI_SSSR_RFS) {
pull_data(dev);
}
if (test_bit_sscr1_tie(spi->regs)) {
if (status & INTEL_SPI_SSSR_TFS) {
push_data(dev);
}
}
out:
completed(dev, error);
}
static const struct spi_driver_api intel_spi_api = {
.transceive = spi_intel_transceive,
#ifdef CONFIG_SPI_ASYNC
.transceive_async = spi_intel_transceive_async,
#endif /* CONFIG_SPI_ASYNC */
.release = spi_intel_release,
};
#ifdef CONFIG_PCI
static inline int spi_intel_setup(struct device *dev)
{
struct spi_intel_data *spi = dev->driver_data;
pci_bus_scan_init();
if (!pci_bus_scan(&spi->pci_dev)) {
LOG_DBG("Could not find device");
return 0;
}
#ifdef CONFIG_PCI_ENUMERATION
spi->regs = spi->pci_dev.addr;
#endif
pci_enable_regs(&spi->pci_dev);
pci_show(&spi->pci_dev);
return 1;
}
#else
#define spi_intel_setup(_unused_) (1)
#endif /* CONFIG_PCI */
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static void spi_intel_set_power_state(struct device *dev, u32_t power_state)
{
struct spi_intel_data *spi = dev->driver_data;
spi->device_power_state = power_state;
}
#else
#define spi_intel_set_power_state(...)
#endif
int spi_intel_init(struct device *dev)
{
const struct spi_intel_config *info = dev->config->config_info;
if (!spi_intel_setup(dev)) {
return -EPERM;
}
info->config_func();
spi_intel_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
irq_enable(info->irq);
LOG_DBG("SPI Intel Driver initialized on device: %p", dev);
return 0;
}
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
static u32_t spi_intel_get_power_state(struct device *dev)
{
struct spi_intel_data *spi = dev->driver_data;
return spi->device_power_state;
}
static int spi_intel_suspend(struct device *dev)
{
const struct spi_intel_config *info = dev->config->config_info;
struct spi_intel_data *spi = dev->driver_data;
LOG_DBG("%p", dev);
clear_bit_sscr0_sse(spi->regs);
irq_disable(info->irq);
spi_intel_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
return 0;
}
static int spi_intel_resume_from_suspend(struct device *dev)
{
const struct spi_intel_config *info = dev->config->config_info;
struct spi_intel_data *spi = dev->driver_data;
LOG_DBG("%p", dev);
set_bit_sscr0_sse(spi->regs);
irq_enable(info->irq);
spi_intel_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
return 0;
}
/*
* Implements the driver control management functionality
* the *context may include IN data or/and OUT data
*/
static int spi_intel_device_ctrl(struct device *dev, u32_t ctrl_command,
void *context, device_pm_cb cb, void *arg)
{
int ret = 0;
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
ret = spi_intel_suspend(dev);
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
ret = spi_intel_resume_from_suspend(dev);
}
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
*((u32_t *)context) = spi_intel_get_power_state(dev);
}
if (cb) {
cb(dev, ret, context, arg);
}
return ret;
}
#else
#define spi_intel_set_power_state(...)
#endif
/* system bindings */
#ifdef CONFIG_SPI_0
void spi_config_0_irq(void);
struct spi_intel_data spi_intel_data_port_0 = {
SPI_CONTEXT_INIT_LOCK(spi_intel_data_port_0, ctx),
SPI_CONTEXT_INIT_SYNC(spi_intel_data_port_0, ctx),
.regs = DT_SPI_0_BASE_ADDRESS,
#if CONFIG_PCI
.pci_dev.class_type = SPI_INTEL_CLASS,
.pci_dev.bus = SPI_INTEL_PORT_0_BUS,
.pci_dev.dev = SPI_INTEL_PORT_0_DEV,
.pci_dev.vendor_id = SPI_INTEL_VENDOR_ID,
.pci_dev.device_id = SPI_INTEL_DEVICE_ID,
.pci_dev.function = SPI_INTEL_PORT_0_FUNCTION,
#endif
};
const struct spi_intel_config spi_intel_config_0 = {
.irq = DT_SPI_0_IRQ,
.config_func = spi_config_0_irq
};
DEVICE_DEFINE(spi_intel_port_0, DT_SPI_0_NAME, spi_intel_init,
spi_intel_device_ctrl, &spi_intel_data_port_0,
&spi_intel_config_0, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&intel_spi_api);
void spi_config_0_irq(void)
{
IRQ_CONNECT(DT_SPI_0_IRQ, DT_SPI_0_IRQ_PRI,
spi_intel_isr, DEVICE_GET(spi_intel_port_0),
DT_SPI_0_IRQ_FLAGS);
}
#endif /* CONFIG_SPI_0 */
#ifdef CONFIG_SPI_1
void spi_config_1_irq(void);
struct spi_intel_data spi_intel_data_port_1 = {
SPI_CONTEXT_INIT_LOCK(spi_intel_data_port_1, ctx),
SPI_CONTEXT_INIT_SYNC(spi_intel_data_port_1, ctx),
.regs = DT_SPI_1_BASE_ADDRESS,
#if CONFIG_PCI
.pci_dev.class_type = SPI_INTEL_CLASS,
.pci_dev.bus = SPI_INTEL_PORT_1_BUS,
.pci_dev.dev = SPI_INTEL_PORT_1_DEV,
.pci_dev.function = SPI_INTEL_PORT_1_FUNCTION,
.pci_dev.vendor_id = SPI_INTEL_VENDOR_ID,
.pci_dev.device_id = SPI_INTEL_DEVICE_ID,
#endif
};
const struct spi_intel_config spi_intel_config_1 = {
.irq = DT_SPI_1_IRQ,
.config_func = spi_config_1_irq
};
DEVICE_DEFINE(spi_intel_port_1, DT_SPI_1_NAME, spi_intel_init,
spi_intel_device_ctrl, &spi_intel_data_port_1,
&spi_intel_config_1, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
&intel_spi_api);
void spi_config_1_irq(void)
{
IRQ_CONNECT(DT_SPI_1_IRQ, DT_SPI_1_IRQ_PRI,
spi_intel_isr, DEVICE_GET(spi_intel_port_1),
DT_SPI_1_IRQ_FLAGS);
}
#endif /* CONFIG_SPI_1 */

102
drivers/spi/spi_intel.h
View file

@ -1,102 +0,0 @@
/* spi_intel.h - Intel's SPI driver private definitions */
/*
* Copyright (c) 2015 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_SPI_SPI_INTEL_H_
#define ZEPHYR_DRIVERS_SPI_SPI_INTEL_H_
#include "spi_intel_regs.h"
#include "spi_context.h"
#ifdef CONFIG_PCI
#include <pci/pci.h>
#include <pci/pci_mgr.h>
#endif /* CONFIG_PCI */
#ifdef __cplusplus
extern "C" {
#endif
typedef void (*spi_intel_config_t)(void);
struct spi_intel_config {
u32_t irq;
spi_intel_config_t config_func;
};
struct spi_intel_data {
struct spi_context ctx;
u32_t regs;
#ifdef CONFIG_PCI
struct pci_dev_info pci_dev;
#endif /* CONFIG_PCI */
u32_t sscr0;
u32_t sscr1;
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
u32_t device_power_state;
#endif
u8_t dfs;
};
#define DEFINE_MM_REG_READ(__reg, __off, __sz) \
static inline u32_t read_##__reg(u32_t addr) \
{ \
return sys_read##__sz(addr + __off); \
}
#define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \
static inline void write_##__reg(u32_t data, u32_t addr) \
{ \
sys_write##__sz(data, addr + __off); \
}
DEFINE_MM_REG_WRITE(sscr0, INTEL_SPI_REG_SSCR0, 32)
DEFINE_MM_REG_WRITE(sscr1, INTEL_SPI_REG_SSCR1, 32)
DEFINE_MM_REG_READ(sssr, INTEL_SPI_REG_SSSR, 32)
DEFINE_MM_REG_READ(ssdr, INTEL_SPI_REG_SSDR, 32)
DEFINE_MM_REG_WRITE(ssdr, INTEL_SPI_REG_SSDR, 32)
DEFINE_MM_REG_WRITE(dds_rate, INTEL_SPI_REG_DDS_RATE, 32)
#define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \
static inline void set_bit_##__reg_bit(u32_t addr) \
{ \
sys_set_bit(addr + __reg_off, __bit); \
}
#define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \
static inline void clear_bit_##__reg_bit(u32_t addr) \
{ \
sys_clear_bit(addr + __reg_off, __bit); \
}
#define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \
static inline int test_bit_##__reg_bit(u32_t addr) \
{ \
return sys_test_bit(addr + __reg_off, __bit); \
}
DEFINE_SET_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
DEFINE_CLEAR_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
DEFINE_TEST_BIT_OP(sscr0_sse, INTEL_SPI_REG_SSCR0, INTEL_SPI_SSCR0_SSE_BIT)
DEFINE_TEST_BIT_OP(sssr_bsy, INTEL_SPI_REG_SSSR, INTEL_SPI_SSSR_BSY_BIT)
DEFINE_CLEAR_BIT_OP(sscr1_tie, INTEL_SPI_REG_SSCR1, INTEL_SPI_SSCR1_TIE_BIT)
DEFINE_TEST_BIT_OP(sscr1_tie, INTEL_SPI_REG_SSCR1, INTEL_SPI_SSCR1_TIE_BIT)
DEFINE_CLEAR_BIT_OP(sssr_ror, INTEL_SPI_REG_SSSR, INTEL_SPI_SSSR_ROR_BIT)
/* 0x38 represents the bits 8, 16 and 32. Knowing that 24 is bits 8 and 16
* These are the bits were when you divide by 8, you keep the result as it is.
* For all the other ones, 4 to 7, 9 to 15, etc... you need a +1,
* since on such division it takes only the result above 0
*/
#define SPI_WS_TO_DFS(__bpw) (((__bpw) & ~0x38) ? \
(((__bpw) / 8) + 1) : \
((__bpw) / 8))
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_SPI_SPI_INTEL_H_ */

80
drivers/spi/spi_intel_regs.h
View file

@ -1,80 +0,0 @@
/*
* Copyright (c) 2015 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_SPI_SPI_INTEL_REGS_H_
#define ZEPHYR_DRIVERS_SPI_SPI_INTEL_REGS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* Intel's SPI driver registers definition */
/* Registers */
#define INTEL_SPI_REG_SSCR0 (0x00)
#define INTEL_SPI_REG_SSCR1 (0x04)
#define INTEL_SPI_REG_SSSR (0x08)
#define INTEL_SPI_REG_SSDR (0x10)
#define INTEL_SPI_REG_DDS_RATE (0x28)
#define INTEL_SPI_CLK_DIV_MASK (0x000000ff)
#define INTEL_SPI_DDS_RATE_MASK (0xffffff00)
/* SSCR0 settings */
#define INTEL_SPI_SSCR0_DSS(__bpw) ((__bpw) - 1)
#define INTEL_SPI_SSCR0_SSE (0x1 << 7)
#define INTEL_SPI_SSCR0_SSE_BIT (7)
#define INTEL_SPI_SSCR0_SCR(__msf) \
((__msf & INTEL_SPI_CLK_DIV_MASK) << 8)
/* SSCR1 settings */
#define INTEL_SPI_SSCR1_TIE_BIT (1)
#define INTEL_SPI_SSCR1_RIE (0x1)
#define INTEL_SPI_SSCR1_TIE (0x1 << 1)
#define INTEL_SPI_SSCR1_LBM (0x1 << 2)
#define INTEL_SPI_SSCR1_SPO (0x1 << 3)
#define INTEL_SPI_SSCR1_SPH (0x1 << 4)
#define INTEL_SPI_SSCR1_TFT_MASK (0x1f << 6)
#define INTEL_SPI_SSCR1_TFT(__tft) \
(((__tft) - 1) << 6)
#define INTEL_SPI_SSCR1_RFT_MASK (0x1f << 11)
#define INTEL_SPI_SSCR1_RFT(__rft) \
(((__rft) - 1) << 11)
#define INTEL_SPI_SSCR1_EFWR (0x1 << 16)
#define INTEL_SPI_SSCR1_STRF (0x1 << 17)
#define INTEL_SPI_SSCR1_TFT_DFLT (8)
#define INTEL_SPI_SSCR1_RFT_DFLT (1)
/* SSSR settings */
#define INTEL_SPI_SSSR_TNF (0x4)
#define INTEL_SPI_SSSR_RNE (0x8)
#define INTEL_SPI_SSSR_TFS (0x20)
#define INTEL_SPI_SSSR_RFS (0x40)
#define INTEL_SPI_SSSR_ROR (0x80)
#define INTEL_SPI_SSSR_TFL_MASK (0x1f << 8)
#define INTEL_SPI_SSSR_TFL_EMPTY (0x00)
#define INTEL_SPI_SSSR_RFL_MASK (0x1f << 13)
#define INTEL_SPI_SSSR_RFL_EMPTY (0x1f)
#define INTEL_SPI_SSSR_TFL(__status) \
((__status & INTEL_SPI_SSSR_TFL_MASK) >> 8)
#define INTEL_SPI_SSSR_RFL(__status) \
((__status & INTEL_SPI_SSSR_RFL_MASK) >> 13)
#define INTEL_SPI_SSSR_BSY_BIT (4)
#define INTEL_SPI_SSSR_ROR_BIT (7)
/* DSS_RATE settings */
#define INTEL_SPI_DSS_RATE(__msf) \
((__msf & (INTEL_SPI_DDS_RATE_MASK)) >> 8)
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_SPI_SPI_INTEL_REGS_H_ */