arm64: cortex_r: Move mpu code to a better place

This patch mainly moves mpu related code from
arch/arm64/core/cortex_r/mpu/ to arch/arm64/core/cortex_r/ and moves
the mpu header files from include/arch/arm64/cortex_r/mpu/ to
include/arch/arm64/cortex_r/

Signed-off-by: Jaxson Han <jaxson.han@arm.com>

arch/arm64/core/CMakeLists.txt

@@ -17,6 +17,7 @@ zephyr_library_sources(
 
 zephyr_library_sources_ifdef(CONFIG_FPU_SHARING fpu.c fpu.S)
 zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu.c mmu.S)
+zephyr_library_sources_ifdef(CONFIG_ARM_MPU cortex_r/arm_mpu.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
 zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
 zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
@@ -28,6 +29,4 @@ if ((CONFIG_MP_NUM_CPUS GREATER 1) OR (CONFIG_SMP))
   zephyr_library_sources(smp.c)
 endif ()
 
-add_subdirectory_ifdef(CONFIG_ARM_MPU cortex_r/mpu)
-
 zephyr_cc_option_ifdef(CONFIG_USERSPACE -mno-outline-atomics)

arch/arm64/core/Kconfig

@@ -137,7 +137,7 @@ config ARMV8_R
 	  Protected Memory System Architecture (PMSA) based on a Memory Protection
 	  Unit (MPU). It supports the A32 and T32 instruction sets.
 
-rsource "cortex_r/mpu/Kconfig"
+rsource "cortex_r/Kconfig"
 
 endif # CPU_AARCH64_CORTEX_R
 

arch/arm64/core/cortex_r/arm_mpu.c

@@ -9,7 +9,7 @@
 #include <init.h>
 #include <kernel.h>
 #include <soc.h>
-#include <arch/arm64/cortex_r/mpu/arm_mpu.h>
+#include <arch/arm64/cortex_r/arm_mpu.h>
 #include <linker/linker-defs.h>
 
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL

arch/arm64/core/cortex_r/mpu/CMakeLists.txt

@@ -1,7 +0,0 @@
-# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
-
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library()
-
-zephyr_library_sources(arm_mpu.c)

include/arch/arm64/cortex_r/arm_mpu.h

@@ -8,7 +8,6 @@
 #ifndef ZEPHYR_INCLUDE_ARCH_ARM64_CORTEX_R_MPU_ARM_MPU_H_
 #define ZEPHYR_INCLUDE_ARCH_ARM64_CORTEX_R_MPU_ARM_MPU_H_
 
-#ifndef _ASMLANGUAGE
 /*
  * Convenience macros to represent the ARMv8-R64-specific configuration
  * for memory access permission and cache-ability attribution.
@@ -183,6 +182,8 @@
 	}
 #endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */
 
+#ifndef _ASMLANGUAGE
+
 struct arm_mpu_region_attr {
 	/* Attributes belonging to PRBAR */
 	uint8_t rbar : 5;

soc/arm64/arm/fvp_aemv8r/arm_mpu_regions.c

@@ -5,7 +5,7 @@
 
 #include <sys/slist.h>
 #include <linker/linker-defs.h>
-#include <arch/arm64/cortex_r/mpu/arm_mpu.h>
+#include <arch/arm64/cortex_r/arm_mpu.h>
 
 
 #define DEVICE_REGION_START 0x80000000UL