michaelh/zephyr
1
0
Fork 0
Code Releases Activity

gpio qmsi: Differentiate between the SoC GPIO and SS GPIO

Browse source 
The SoC level peripherals are accesible by both cores, while the SS
ones are only available to the sensor subsystem. Since the ARC core can
make use of both drivers at the same time, we need to be able to
differentiate their configuration values somehow.

Also disable the SoC GPIO for the ARC by default, as it still needs
more changes to be usable.

Jira: ZEP-1030
Change-Id: Ic5415c404ecd32a3e560467b6f5eaa873a515d72
Signed-off-by: Iván Briano <ivan.briano@intel.com>
This commit is contained in:
Iván Briano 2016-10-18 14:37:47 -02:00 • committed by Anas Nashif
commit 34cf9773b1
3 changed files with 96 additions and 27 deletions
Download patch file Download diff file Expand all files Collapse all files

33
arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig
View file

@ -82,10 +82,10 @@ endif # RTC
if GPIO
config GPIO_QMSI_SS
def_bool y
config GPIO_QMSI
def_bool n
if GPIO_QMSI_SS
if GPIO_QMSI
config GPIO_QMSI_0
def_bool y
@ -109,6 +109,33 @@ endif # GPIO_QMSI_1
endif # GPIO_QMSI
config GPIO_QMSI_SS
def_bool y
if GPIO_QMSI_SS
config GPIO_QMSI_SS_0
def_bool y
if GPIO_QMSI_SS_0
config GPIO_QMSI_SS_0_IRQ_PRI
default 1
endif # GPIO_QMSI_SS_0
config GPIO_QMSI_SS_1
def_bool y
if GPIO_QMSI_SS_1
config GPIO_QMSI_SS_1_IRQ_PRI
default 1
endif # GPIO_QMSI_SS_1
endif # GPIO_QMSI_SS
endif # GPIO

58
drivers/gpio/Kconfig.qmsi
View file

@ -26,11 +26,11 @@ menuconfig GPIO_QMSI
menuconfig GPIO_QMSI_SS
bool "QMSI GPIO SS driver"
depends on GPIO && QMSI
depends on GPIO && QMSI && ARC
default n
help
Enable the GPIO driver found on Intel Microcontroller
boards, using the QMSI library.
boards, on the sensor subsystem, using the QMSI library.
if GPIO_QMSI || GPIO_QMSI_SS
@ -42,6 +42,16 @@ config GPIO_QMSI_INIT_PRIORITY
help
Device driver initialization priority.
config GPIO_QMSI_API_REENTRANCY
bool
prompt "GPIO driver API reentrancy"
depends on GPIO_QMSI
default n
help
Enable support for QMSI GPIO driver API reentrancy.
if GPIO_QMSI
config GPIO_QMSI_0
bool "QMSI GPIO block 0"
default n
@ -76,12 +86,44 @@ config GPIO_QMSI_1_IRQ_PRI
help
IRQ priority
config GPIO_QMSI_API_REENTRANCY
bool
prompt "GPIO driver API reentrancy"
depends on GPIO_QMSI
endif # GPIO_QMSI
if GPIO_QMSI_SS
config GPIO_QMSI_SS_0
bool "QMSI GPIO SS block 0"
default n
help
Enable support for QMSI GPIO driver API reentrancy.
Include support for the GPIO SS port 0 using QMSI.
endif # GPIO_QMSI
config GPIO_QMSI_SS_0_NAME
string "Driver name"
depends on GPIO_QMSI_SS_0
default "GPIO_SS_0"
config GPIO_QMSI_SS_0_IRQ_PRI
int "Controller interrupt priority"
depends on GPIO_QMSI_SS_0
help
IRQ priority
config GPIO_QMSI_SS_1
bool "QMSI GPIO SS block 1"
default n
help
Include support for the GPIO SS port 1 using QMSI.
config GPIO_QMSI_SS_1_NAME
string "Driver name"
depends on GPIO_QMSI_SS_1
default "GPIO_SS_1"
config GPIO_QMSI_SS_1_IRQ_PRI
int "Controller interrupt priority"
depends on GPIO_QMSI_SS_1
help
IRQ priority
endif # GPIO_QMSI_SS
endif # GPIO_QMSI || GPIO_QMSI_SS

32
drivers/gpio/gpio_qmsi_ss.c
View file

@ -76,7 +76,7 @@ static void gpio_critical_region_end(struct device *dev)
static int ss_gpio_qmsi_init(struct device *dev);
#ifdef CONFIG_GPIO_QMSI_0
#ifdef CONFIG_GPIO_QMSI_SS_0
static const struct ss_gpio_qmsi_config ss_gpio_0_config = {
.gpio = QM_SS_GPIO_0,
.num_pins = QM_SS_GPIO_NUM_PINS,
@ -84,13 +84,13 @@ static const struct ss_gpio_qmsi_config ss_gpio_0_config = {
static struct ss_gpio_qmsi_runtime ss_gpio_0_runtime;
DEVICE_INIT(ss_gpio_0, CONFIG_GPIO_QMSI_0_NAME, &ss_gpio_qmsi_init,
DEVICE_INIT(ss_gpio_0, CONFIG_GPIO_QMSI_SS_0_NAME, &ss_gpio_qmsi_init,
&ss_gpio_0_runtime, &ss_gpio_0_config,
SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
#endif /* CONFIG_GPIO_QMSI_0 */
#endif /* CONFIG_GPIO_QMSI_SS_0 */
#ifdef CONFIG_GPIO_QMSI_1
#ifdef CONFIG_GPIO_QMSI_SS_1
static const struct ss_gpio_qmsi_config ss_gpio_1_config = {
.gpio = QM_SS_GPIO_1,
.num_pins = QM_SS_GPIO_NUM_PINS,
@ -98,11 +98,11 @@ static const struct ss_gpio_qmsi_config ss_gpio_1_config = {
static struct ss_gpio_qmsi_runtime gpio_1_runtime;
DEVICE_INIT(ss_gpio_1, CONFIG_GPIO_QMSI_1_NAME, &ss_gpio_qmsi_init,
DEVICE_INIT(ss_gpio_1, CONFIG_GPIO_QMSI_SS_1_NAME, &ss_gpio_qmsi_init,
&gpio_1_runtime, &ss_gpio_1_config,
SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
#endif /* CONFIG_GPIO_QMSI_1 */
#endif /* CONFIG_GPIO_QMSI_SS_1 */
static void ss_gpio_qmsi_callback(void *data, uint32_t status)
{
@ -135,16 +135,16 @@ static inline void ss_qmsi_pin_config(struct device *port, uint32_t pin,
qm_ss_gpio_port_config_t cfg = { 0 };
switch (gpio) {
#ifdef CONFIG_GPIO_QMSI_0
#ifdef CONFIG_GPIO_QMSI_SS_0
case QM_SS_GPIO_0:
controller = QM_SS_GPIO_0_BASE;
break;
#endif /* CONFIG_GPIO_QMSI_0 */
#ifdef CONFIG_GPIO_QMSI_1
#endif /* CONFIG_GPIO_QMSI_SS_0 */
#ifdef CONFIG_GPIO_QMSI_SS_1
case QM_SS_GPIO_1:
controller = QM_SS_GPIO_1_BASE;
break;
#endif /* CONFIG_GPIO_QMSI_1 */
#endif /* CONFIG_GPIO_QMSI_SS_1 */
default:
return;
}
@ -316,10 +316,10 @@ static int ss_gpio_qmsi_init(struct device *port)
gpio_reentrancy_init(port);
switch (gpio_config->gpio) {
#ifdef CONFIG_GPIO_QMSI_0
#ifdef CONFIG_GPIO_QMSI_SS_0
case QM_SS_GPIO_0:
IRQ_CONNECT(IRQ_GPIO0_INTR,
CONFIG_GPIO_QMSI_0_IRQ_PRI, ss_gpio_isr,
CONFIG_GPIO_QMSI_SS_0_IRQ_PRI, ss_gpio_isr,
DEVICE_GET(ss_gpio_0), 0);
irq_enable(IRQ_GPIO0_INTR);
@ -329,11 +329,11 @@ static int ss_gpio_qmsi_init(struct device *port)
(uint32_t *)&QM_INTERRUPT_ROUTER->ss_gpio_0_int_mask;
*scss_intmask &= ~BIT(8);
break;
#endif /* CONFIG_GPIO_QMSI_0 */
#ifdef CONFIG_GPIO_QMSI_1
#endif /* CONFIG_GPIO_QMSI_SS_0 */
#ifdef CONFIG_GPIO_QMSI_SS_1
case QM_SS_GPIO_1:
IRQ_CONNECT(IRQ_GPIO1_INTR,
CONFIG_GPIO_QMSI_1_IRQ_PRI, ss_gpio_isr,
CONFIG_GPIO_QMSI_SS_1_IRQ_PRI, ss_gpio_isr,
DEVICE_GET(ss_gpio_1), 0);
irq_enable(IRQ_GPIO1_INTR);
@ -343,7 +343,7 @@ static int ss_gpio_qmsi_init(struct device *port)
(uint32_t *)&QM_INTERRUPT_ROUTER->ss_gpio_1_int_mask;
*scss_intmask &= ~BIT(8);
break;
#endif /* CONFIG_GPIO_QMSI_1 */
#endif /* CONFIG_GPIO_QMSI_SS_1 */
default:
return -EIO;
}