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soc: smartbond: da1469x: Support Global Foundries silicon

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Add support for the GF silicon variant.

Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
This commit is contained in:
Ioannis Karachalios 2023-07-22 09:51:25 +03:00 • committed by Carles Cufí
commit 34ce476ce6
1 changed files with 41 additions and 5 deletions
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46
soc/arm/renesas_smartbond/da1469x/soc.c
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@ -8,6 +8,12 @@
#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h> #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
#include <zephyr/linker/linker-defs.h> #include <zephyr/linker/linker-defs.h>
#include <string.h> #include <string.h>
#include <DA1469xAB.h>
#include <da1469x_clock.h>
#include <da1469x_otp.h>
#include <da1469x_pd.h>
#include <da1469x_pdc.h>
#include <da1469x_trimv.h>
#define REMAP_ADR0_QSPI 0x2 #define REMAP_ADR0_QSPI 0x2
@ -107,17 +113,47 @@ void z_arm_platform_init(void)
#endif #endif
} }
static int renesas_da14699_init(void) static int renesas_da1469x_init(void)
{ {
/* Freeze watchdog until configured */ /* Freeze watchdog until configured */
GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk; GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
/* Reset clock dividers to 0 */ /* Reset clock dividers to 0 */
CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk | CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk |
CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk); CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
/* Enable all power domains except for radio */
CRG_TOP->PMU_CTRL_REG = 0x02; CRG_TOP->PMU_CTRL_REG |= (CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Msk |
CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk |
CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Msk |
CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk);
/* PDC should take care of PD_SYS */
CRG_TOP->PMU_CTRL_REG &= ~CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Msk;
/*
* Due to crosstalk issues any power rail can potentially
* issue a fake event. This is typically observed upon
* switching power sources, that is DCDC <--> LDOs <--> Retention LDOs.
*/
CRG_TOP->BOD_CTRL_REG &= ~(CRG_TOP_BOD_CTRL_REG_BOD_V14_EN_Msk |
CRG_TOP_BOD_CTRL_REG_BOD_V18F_EN_Msk |
CRG_TOP_BOD_CTRL_REG_BOD_VDD_EN_Msk |
CRG_TOP_BOD_CTRL_REG_BOD_V18P_EN_Msk |
CRG_TOP_BOD_CTRL_REG_BOD_V18_EN_Msk |
CRG_TOP_BOD_CTRL_REG_BOD_V30_EN_Msk |
CRG_TOP_BOD_CTRL_REG_BOD_VBAT_EN_Msk);
da1469x_pdc_reset();
da1469x_otp_init();
da1469x_trimv_init_from_otp();
da1469x_pd_init();
da1469x_pd_acquire(MCU_PD_DOMAIN_SYS);
da1469x_pd_acquire(MCU_PD_DOMAIN_TIM);
da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
return 0; return 0;
} }
SYS_INIT(renesas_da14699_init, PRE_KERNEL_1, 0); SYS_INIT(renesas_da1469x_init, PRE_KERNEL_1, 0);