diff --git a/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts b/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts
index 11f740b2ba2..c1a90a7d1cd 100644
--- a/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts
+++ b/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts
@@ -14,9 +14,43 @@
 
 	chosen {
 		zephyr,sram = &m4_dtcm;
-		zephyr,flash = &ri5cy_code_partition;
+		zephyr,flash = &m4_flash;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
 		zephyr,uart-pipe = &uart0;
+		zephyr,code-partition = &slot0_partition;
+	};
+};
+
+&m4_flash {
+	/*
+	 * For more information, see:
+	 * http://docs.zephyrproject.org/latest/guides/dts/index.html
+	 */
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		slot0_partition: partition@0 {
+			label = "image-0";
+			reg = <0x00000000 0x000069000>;
+		};
+		slot1_partition: partition@69000 {
+			label = "image-1";
+			reg = <0x00069000 0x000069000>;
+		};
+		scratch_partition: partition@d2000 {
+			label = "image-scratch";
+			reg = <0x000d2000 0x0001e000>;
+		};
+		storage_partition: partition@f0000 {
+			label = "storage";
+			reg = <0x000f0000 0x00004000>;
+		};
+		boot_partition: partition@f4000 {
+			label = "mcuboot";
+			reg = <0x000f4000 0x0000C000>;
+		};
 	};
 };
diff --git a/soc/riscv32/openisa_rv32m1/dts_fixup.h b/soc/riscv32/openisa_rv32m1/dts_fixup.h
index decc3ac1ee3..fd3efcb7f30 100644
--- a/soc/riscv32/openisa_rv32m1/dts_fixup.h
+++ b/soc/riscv32/openisa_rv32m1/dts_fixup.h
@@ -10,6 +10,7 @@
 
 #define DT_FLASH_DEV_BASE_ADDRESS DT_OPENISA_RV32M1_FTFE_40023000_BASE_ADDRESS
 #define DT_FLASH_DEV_NAME         DT_OPENISA_RV32M1_FTFE_40023000_LABEL
+#define DT_START_UP_ENTRY_OFFSET  0x80
 
 #endif /* CONFIG_SOC_OPENISA_RV32M1_RISCV32 */
 
diff --git a/soc/riscv32/openisa_rv32m1/linker.ld b/soc/riscv32/openisa_rv32m1/linker.ld
index ddbd7566fa2..8fe0aa6049a 100644
--- a/soc/riscv32/openisa_rv32m1/linker.ld
+++ b/soc/riscv32/openisa_rv32m1/linker.ld
@@ -29,12 +29,38 @@
 #define ROMABLE_REGION              ROM
 #define RAMABLE_REGION              RAM
 
+#define VECTOR_SIZE CONFIG_RISCV32_RV32M1_VECTOR_SIZE
+
+#ifdef CONFIG_USE_CODE_PARTITION
+
+#ifdef CONFIG_BOOTLOADER_MCUBOOT
+
+
+#define ROM_BASE (DT_CODE_PARTITION_OFFSET)
+#define ROM_SIZE (DT_CODE_PARTITION_SIZE)
+
+#define VECTOR_BASE (ROM_BASE + CONFIG_TEXT_SECTION_OFFSET)
+
+#else
+
+#define ROM_BASE DT_CODE_PARTITION_OFFSET
+#define ROM_SIZE (DT_CODE_PARTITION_SIZE - VECTOR_SIZE)
+
+#define VECTOR_BASE (ROM_BASE + ROM_SIZE)
+
+#endif
+
+#else
+
 #define ROM_BASE DT_FLASH_BASE_ADDRESS
-#define ROM_SIZE KB(DT_FLASH_SIZE)
+#define ROM_SIZE (KB(DT_FLASH_SIZE) - VECTOR_SIZE)
+
+#define VECTOR_BASE (ROM_BASE + ROM_SIZE)
+
+#endif
+
 #define RAM_BASE DT_SRAM_BASE_ADDRESS
 #define RAM_SIZE KB(DT_SRAM_SIZE)
-#define VECTOR_BASE CONFIG_RISCV32_RV32M1_VECTOR_BASE_ADDR
-#define VECTOR_SIZE CONFIG_RISCV32_RV32M1_VECTOR_SIZE
 
 MEMORY
     {
@@ -47,7 +73,9 @@ MEMORY
      * (The Arm core vector tables are at the beginning of each
      * flash bank.)
      */
+#ifndef CONFIG_BOOTLOADER_MCUBOOT
     VECTORS (rx)  : ORIGIN = VECTOR_BASE, LENGTH = VECTOR_SIZE
+#endif
     RAM (rwx)     : ORIGIN = RAM_BASE,    LENGTH = RAM_SIZE
     /*
      * Special section, not included in the final binary, used
@@ -86,6 +114,20 @@ SECTIONS
 	 * for MCUboot support, so .reset.* and .exception.*
 	 * must come after that offset from ROM_BASE.
 	 */
+
+#ifdef CONFIG_BOOTLOADER_MCUBOOT
+	/*
+	 * For CONFIG_BOOTLOADER_MCUBOOT, the vector table is located at the
+	 * end of the image header of the MCUboot. After the tagert image is
+	 * boot, the register Machine Trap-Vector Base Address (MTVEC) is
+	 * set with the value of _vector_start in the reset handler.
+	 */
+	_vector_start = .;
+	KEEP(*(.vectors.*))
+	_vector_end = .;
+	. = ALIGN(4);
+#endif
+
 	KEEP(*(.reset.*))
 	KEEP(*(".exception.entry.*")) /* contains __irq_wrapper */
 	*(".exception.other.*")
@@ -124,6 +166,7 @@ SECTIONS
     _image_rodata_end = .;
     _image_rom_end = .;
 
+#ifndef CONFIG_BOOTLOADER_MCUBOOT
     /* The vector table goes into core-dependent flash locations. */
     SECTION_PROLOGUE(vectors,,)
 	{
@@ -131,6 +174,7 @@ SECTIONS
 	KEEP(*(.vectors.*))
 	} GROUP_LINK_IN(VECTORS)
     _vector_end = .;
+#endif
 
     GROUP_END(ROM)