soc: RT685: Add USB support

1. Update soc.c file to add USB clock setup
2. Add a linker script file to move USB transfer
   buffer and controller buffers to USB RAM
3. Update Kconfig's to add USB support
4. Add zephyr_udc0 nodelabel

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>

boards/arm/mimxrt685_evk/doc/index.rst

@@ -93,6 +93,8 @@ features:
 +-----------+------------+-------------------------------------+
 | SDHC      | on-chip    | disk access                         |
 +-----------+------------+-------------------------------------+
+| USB       | on-chip    | USB device                          |
++-----------+------------+-------------------------------------+
 
 The default configuration can be found in the defconfig file:
 

boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts

@@ -302,3 +302,7 @@ i2s1: &flexcomm3 {
 	status = "okay";
 	pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
 };
+
+zephyr_udc0: &usbhs {
+	status = "okay";
+};

boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml

@@ -28,3 +28,4 @@ supported:
   - sdhc
   - spi
   - watchdog
+  - usb_device

soc/arm/nxp_imx/rt6xx/CMakeLists.txt

@@ -22,3 +22,6 @@ zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT6XX_BOOT_HEADER
 
 zephyr_linker_sources(
   RWDATA quick_access.ld)
+
+zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER
+  SECTIONS usb.ld)

soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt685_cm33

@@ -66,4 +66,12 @@ config WDT_MCUX_WWDT
 	default y
 	depends on WATCHDOG
 
+config USB_MCUX
+	default y
+	depends on USB_DEVICE_DRIVER
+
+choice USB_MCUX_CONTROLLER_TYPE
+	default USB_DC_NXP_LPCIP3511
+endchoice
+
 endif # SOC_MIMXRT685S_CM33

soc/arm/nxp_imx/rt6xx/Kconfig.soc

@@ -28,6 +28,8 @@ config SOC_MIMXRT685S_CM33
 	select HAS_MCUX_USDHC1
 	select HAS_MCUX_USDHC2
 	select INIT_SYS_PLL
+	select HAS_MCUX_USB_LPCIP3511
+	select USB_DEDICATED_MEMORY if USB_DEVICE_DRIVER
 
 endchoice
 
@@ -59,6 +61,9 @@ config INIT_SYS_PLL
 config INIT_AUDIO_PLL
 	bool "Initialize Audio PLL"
 
+config USB_DEDICATED_MEMORY
+	bool "Dedicated memory for USB transfer buffer and controller operation buffers"
+
 config XTAL_SYS_CLK_HZ
 	int "External oscillator frequency"
 	help

soc/arm/nxp_imx/rt6xx/soc.c

@@ -25,6 +25,12 @@
 #include <fsl_common.h>
 #include <fsl_device_registers.h>
 
+#if CONFIG_USB_DC_NXP_LPCIP3511
+#include "usb_phy.h"
+#include "usb_dc_mcux.h"
+#endif
+
+
 #define SYSTEM_IS_XIP_FLEXSPI() \
 	((((uint32_t)nxp_rt600_init >= 0x08000000U) &&		\
 	  ((uint32_t)nxp_rt600_init < 0x10000000U)) ||		\
@@ -49,6 +55,13 @@ const clock_audio_pll_config_t g_audioPllConfig = {
 };
 #endif
 
+#if CONFIG_USB_DC_NXP_LPCIP3511
+/* USB PHY condfiguration */
+#define BOARD_USB_PHY_D_CAL (0x0CU)
+#define BOARD_USB_PHY_TXCAL45DP (0x06U)
+#define BOARD_USB_PHY_TXCAL45DM (0x06U)
+#endif
+
 #ifdef CONFIG_NXP_IMX_RT6XX_BOOT_HEADER
 extern char z_main_stack[];
 extern char _flash_used[];
@@ -94,6 +107,63 @@ __imx_boot_ivt_section void (* const image_vector_table[])(void)  = {
 };
 #endif /* CONFIG_NXP_IMX_RT6XX_BOOT_HEADER */
 
+#if CONFIG_USB_DC_NXP_LPCIP3511
+
+static void usb_device_clock_init(void)
+{
+	uint8_t usbClockDiv = 1;
+	uint32_t usbClockFreq;
+	usb_phy_config_struct_t phyConfig = {
+		BOARD_USB_PHY_D_CAL,
+		BOARD_USB_PHY_TXCAL45DP,
+		BOARD_USB_PHY_TXCAL45DM,
+	};
+
+	/* enable USB IP clock */
+	CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 5);
+	CLOCK_AttachClk(kXTALIN_CLK_to_USB_CLK);
+	CLOCK_SetClkDiv(kCLOCK_DivUsbHsFclk, usbClockDiv);
+	CLOCK_EnableUsbhsDeviceClock();
+	RESET_PeripheralReset(kUSBHS_PHY_RST_SHIFT_RSTn);
+	RESET_PeripheralReset(kUSBHS_DEVICE_RST_SHIFT_RSTn);
+	RESET_PeripheralReset(kUSBHS_HOST_RST_SHIFT_RSTn);
+	RESET_PeripheralReset(kUSBHS_SRAM_RST_SHIFT_RSTn);
+	/*Make sure USDHC ram buffer has power up*/
+	POWER_DisablePD(kPDRUNCFG_APD_USBHS_SRAM);
+	POWER_DisablePD(kPDRUNCFG_PPD_USBHS_SRAM);
+	POWER_ApplyPD();
+
+	/* save usb ip clock freq*/
+	usbClockFreq = g_xtalFreq / usbClockDiv;
+	/* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */
+	CLOCK_EnableUsbHs0PhyPllClock(kXTALIN_CLK_to_USB_CLK, usbClockFreq);
+
+#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM)
+	for (int i = 0; i < FSL_FEATURE_USBHSD_USB_RAM; i++) {
+		((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)[i] = 0x00U;
+	}
+#endif
+	USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, CLK_XTAL_OSC_CLK, &phyConfig);
+
+	/* the following code should run after phy initialization and
+	 * should wait some microseconds to make sure utmi clock valid
+	 */
+	/* enable usb1 host clock */
+	CLOCK_EnableClock(kCLOCK_UsbhsHost);
+	/* Wait until host_needclk de-asserts */
+	while (SYSCTL0->USBCLKSTAT & SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST_MASK) {
+		__ASM("nop");
+	}
+	/* According to reference mannual, device mode setting has to be set by
+	 * access usb host register
+	 */
+	USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
+	/* disable usb1 host clock */
+	CLOCK_DisableClock(kCLOCK_UsbhsHost);
+}
+
+#endif
+
 /**
  *
  * @brief Initialize the system clock
@@ -101,7 +171,6 @@ __imx_boot_ivt_section void (* const image_vector_table[])(void)  = {
  * @return N/A
  *
  */
-
 static ALWAYS_INLINE void clock_init(void)
 {
 #ifdef CONFIG_SOC_MIMXRT685S_CM33
@@ -151,6 +220,10 @@ static ALWAYS_INLINE void clock_init(void)
 
 	CLOCK_AttachClk(kSFRO_to_FLEXCOMM0);
 
+#if CONFIG_USB_DC_NXP_LPCIP3511
+	usb_device_clock_init();
+#endif
+
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_i2c, okay)
 	CLOCK_AttachClk(kSFRO_to_FLEXCOMM2);
 #endif

soc/arm/nxp_imx/rt6xx/usb.ld

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+GROUP_START(USB_BDT)
+
+	SECTION_PROLOGUE(_USB_BDT_SECTION_NAME,(NOLOAD),)
+	{
+		. = ALIGN(512);
+		*(m_usb_bdt)
+	} GROUP_LINK_IN(SRAM1)
+
+GROUP_END(USB_BDT)
+
+GROUP_START(USB_GLOBAL)
+
+	SECTION_PROLOGUE(_USB_GLOBAL_SECTION_NAME,(NOLOAD),)
+	{
+		*(m_usb_global)
+	} GROUP_LINK_IN(SRAM1)
+
+GROUP_END(USB_GLOBAL)