x86: 32-bit: restore virtual linking capability
This reverts commit 7d32e9f9a5.
We now allow the kernel to be linked virtually. This patch:
- Properly converts between virtual/physical addresses
- Handles early boot instruction pointer transition
- Double-maps SRAM to both virtual and physical locations
in boot page tables to facilitate instruction pointer
transition, with logic to clean this up after completed.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Andrew Boie
Anas Nashif
parent
03b413712a
commit
348d1315d2
6 changed files with 110 additions and 55 deletions
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@ -21,6 +21,7 @@
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#include <arch/cpu.h>
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#include <arch/x86/multiboot.h>
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#include <x86_mmu.h>
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#include <sys/mem_manage.h>
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/* exports (private APIs) */
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@ -43,6 +44,51 @@
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GDATA(_sse_mxcsr_default_value)
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#endif
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.macro install_page_tables
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#ifdef CONFIG_X86_MMU
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/* Enable paging. If virtual memory is enabled, the instruction pointer
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* is currently at a physical address. There is an identity mapping
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* for all RAM, plus a virtual mapping of RAM starting at
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* CONFIG_KERNEL_VM_BASE using the same paging structures.
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*
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* Until we enable these page tables, only physical memory addresses
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* work.
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*/
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movl $Z_MEM_PHYS_ADDR(z_x86_kernel_ptables), %eax
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movl %eax, %cr3
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#ifdef CONFIG_X86_PAE
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/* Enable PAE */
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movl %cr4, %eax
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orl $CR4_PAE, %eax
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movl %eax, %cr4
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/* IA32_EFER NXE bit set */
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movl $0xC0000080, %ecx
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rdmsr
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orl $0x800, %eax
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wrmsr
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#endif /* CONFIG_X86_PAE */
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/* Enable paging (CR0.PG, bit 31) / write protect (CR0.WP, bit 16) */
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movl %cr0, %eax
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orl $(CR0_PG | CR0_WP), %eax
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movl %eax, %cr0
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#ifdef Z_VM_KERNEL
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/* Jump to a virtual address, which works because the identity and
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* virtual mappings both are to the same physical address.
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*/
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ljmp $CODE_SEG, $vm_enter
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vm_enter:
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/* We are now executing in virtual memory. We'll un-map the identity
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* mappings later once we are in the C domain
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*/
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#endif /* Z_VM_KERNEL */
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#endif /* CONFIG_X86_MMU */
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.endm
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SECTION_FUNC(TEXT_START, __start)
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#include "../common.S"
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@ -158,9 +204,6 @@ __csSet:
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addl $CONFIG_ISR_STACK_SIZE, %esp
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#endif
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/* Clear BSS */
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call z_bss_zero
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#ifdef CONFIG_XIP
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/* Copy data from flash to RAM.
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*
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@ -179,53 +222,18 @@ __csSet:
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mov $MAIN_TSS, %ax
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ltr %ax
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#endif
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/* load 32-bit operand size IDT */
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lidt Z_MEM_PHYS_ADDR(z_x86_idt)
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#ifdef CONFIG_X86_MMU
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/* Install page tables */
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movl $Z_MEM_PHYS_ADDR(z_x86_kernel_ptables), %eax
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movl %eax, %cr3
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#ifdef CONFIG_X86_PAE
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/* Enable PAE */
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movl %cr4, %eax
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orl $CR4_PAE, %eax
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movl %eax, %cr4
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/* IA32_EFER NXE bit set */
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movl $0xC0000080, %ecx
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rdmsr
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orl $0x800, %eax
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wrmsr
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#endif /* CONFIG_X86_PAE */
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/* Enable paging (CR0.PG, bit 31) / write protect (CR0.WP, bit 16) */
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movl %cr0, %eax
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orl $(CR0_PG | CR0_WP), %eax
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movl %eax, %cr0
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#endif /* CONFIG_X86_MMU */
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#if (Z_MEM_PHYS_ADDR(0x1000) != 0x1000)
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/*
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* Page table loaded so we can start executing in
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* virtual address space.
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*
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* Note that __prep_c and z_x86_prep_c() must be
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* mapped in virtual address space in gen_mmu.py.
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*
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* This jump must be done due to relative
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* addressing code emitted by the toolchain
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* (think EIP + offset). If we are not already in
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* virtual address space, everything afterwards
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* would still be referenced via physical addresses
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* and will crash if we have a kernel bigger than
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* physical memory with demand paging (for example).
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/* Note that installing page tables must be done after
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* z_data_copy() as the page tables are being copied into
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* RAM there.
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*/
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ljmp $CODE_SEG, $__prep_c
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install_page_tables
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__prep_c:
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#endif
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/* Clear BSS */
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call z_bss_zero
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/* load 32-bit operand size IDT */
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lidt z_x86_idt
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pushl %ebx /* pointer to multiboot info, or NULL */
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call z_x86_prep_c /* enter kernel; never returns */
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@ -250,8 +258,8 @@ z_x86_idt:
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* setup by the BIOS (or GRUB?).
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*/
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/* physical start address */
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.long Z_MEM_PHYS_ADDR(_idt_base_address)
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/* IDT table start address */
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.long _idt_base_address
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#ifdef CONFIG_SET_GDT
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@ -42,7 +42,7 @@
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/* Page tables created at build time by gen_mmu.py
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* NOTE: Presumes phys=virt
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*/
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movl $z_x86_kernel_ptables, %eax
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movl $Z_MEM_PHYS_ADDR(z_x86_kernel_ptables), %eax
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movl %eax, %cr3
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set_efer
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@ -64,7 +64,7 @@
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clts
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/* NOTE: Presumes phys=virt */
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movq $z_x86_kernel_ptables, %rax
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movq $Z_MEM_PHYS_ADDR(z_x86_kernel_ptables), %rax
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movq %rax, %cr3
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set_efer
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@ -87,7 +87,7 @@ z_x86_syscall_entry_stub:
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pushq %rax
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/* NOTE: Presumes phys=virt */
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movq $z_x86_kernel_ptables, %rax
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movq $Z_MEM_PHYS_ADDR(z_x86_kernel_ptables), %rax
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movq %rax, %cr3
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popq %rax
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movq $0, -8(%rsp) /* Delete stashed RAX data */
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@ -40,6 +40,10 @@ FUNC_NORETURN void z_x86_prep_c(void *arg)
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ARG_UNUSED(info);
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#endif
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#ifdef CONFIG_MMU
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z_x86_mmu_init();
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#endif
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#if CONFIG_X86_STACK_PROTECTION
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for (int i = 0; i < CONFIG_MP_NUM_CPUS; i++) {
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z_x86_set_stack_guard(z_interrupt_stacks[i]);
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@ -517,9 +517,12 @@ static void print_entries(pentry_t entries_array[], uint8_t *base, int level,
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if (phys == virt) {
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/* Identity mappings */
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COLOR(YELLOW);
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} else {
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/* Other mappings */
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} else if (phys + Z_MEM_VM_OFFSET == virt) {
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/* Permanent RAM mappings */
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COLOR(GREEN);
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} else {
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/* General mapped pages */
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COLOR(CYAN);
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}
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} else {
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/* Intermediate entry */
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@ -580,7 +583,8 @@ static void dump_ptables(pentry_t *table, uint8_t *base, int level)
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}
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#endif
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printk("%s at %p: ", info->name, table);
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printk("%s at %p (0x%" PRIxPTR "): ", info->name, table,
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z_mem_phys_addr(table));
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if (level == 0) {
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printk("entire address space\n");
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} else {
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@ -1111,6 +1115,42 @@ void arch_mem_map(void *virt, uintptr_t phys, size_t size, uint32_t flags)
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MASK_ALL, 0);
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}
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static void identity_map_remove(void)
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{
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#ifdef Z_VM_KERNEL
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size_t size, scope = get_entry_scope(0);
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uint8_t *pos;
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k_mem_region_align((uintptr_t *)&pos, &size,
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(uintptr_t)CONFIG_SRAM_BASE_ADDRESS,
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(size_t)CONFIG_SRAM_SIZE * 1024U, scope);
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/* We booted with RAM mapped both to its identity and virtual
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* mapping starting at CONFIG_KERNEL_VM_BASE. This was done by
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* double-linking the relevant tables in the top-level table.
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* At this point we don't need the identity mapping(s) any more,
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* zero the top-level table entries corresponding to the
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* physical mapping.
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*/
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while (size) {
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pentry_t *entry = get_entry_ptr(z_x86_kernel_ptables, pos, 0);
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/* set_pte */
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*entry = 0;
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pos += scope;
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size -= scope;
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}
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#endif
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}
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/* Invoked to remove the identity mappings in the page tables,
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* they were only needed to tranisition the instruction pointer at early boot
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*/
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void z_x86_mmu_init(void)
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{
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identity_map_remove();
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}
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#if CONFIG_X86_STACK_PROTECTION
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void z_x86_set_stack_guard(k_thread_stack_t *stack)
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{
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@ -229,5 +229,8 @@ void z_x86_tlb_ipi(const void *arg);
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#ifdef CONFIG_X86_COMMON_PAGE_TABLE
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void z_x86_swap_update_common_page_table(struct k_thread *incoming);
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#endif
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/* Early-boot paging setup tasks, called from prep_c */
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void z_x86_mmu_init(void);
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_ARCH_X86_INCLUDE_X86_MMU_H */
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