From 346836b24b0cfb0f91276a16165beb13c62d2ab7 Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Mon, 19 Dec 2022 00:15:51 +0900 Subject: [PATCH] boards: riscv: add M5Stack STAMP-C3 Add M5Stack STAMP-C3 an ESP32-C3 based board. Signed-off-by: TOKITA Hiroshi --- boards/riscv/stamp_c3/Kconfig.board | 8 ++ boards/riscv/stamp_c3/Kconfig.defconfig | 21 +++ boards/riscv/stamp_c3/board.cmake | 9 ++ boards/riscv/stamp_c3/doc/index.rst | 124 ++++++++++++++++ boards/riscv/stamp_c3/stamp_c3-pinctrl.dtsi | 51 +++++++ boards/riscv/stamp_c3/stamp_c3.dts | 150 ++++++++++++++++++++ boards/riscv/stamp_c3/stamp_c3.yaml | 16 +++ boards/riscv/stamp_c3/stamp_c3_defconfig | 12 ++ boards/riscv/stamp_c3/support/openocd.cfg | 9 ++ 9 files changed, 400 insertions(+) create mode 100644 boards/riscv/stamp_c3/Kconfig.board create mode 100644 boards/riscv/stamp_c3/Kconfig.defconfig create mode 100644 boards/riscv/stamp_c3/board.cmake create mode 100644 boards/riscv/stamp_c3/doc/index.rst create mode 100644 boards/riscv/stamp_c3/stamp_c3-pinctrl.dtsi create mode 100644 boards/riscv/stamp_c3/stamp_c3.dts create mode 100644 boards/riscv/stamp_c3/stamp_c3.yaml create mode 100644 boards/riscv/stamp_c3/stamp_c3_defconfig create mode 100644 boards/riscv/stamp_c3/support/openocd.cfg diff --git a/boards/riscv/stamp_c3/Kconfig.board b/boards/riscv/stamp_c3/Kconfig.board new file mode 100644 index 00000000000..314bbeb0ce7 --- /dev/null +++ b/boards/riscv/stamp_c3/Kconfig.board @@ -0,0 +1,8 @@ +# M5Stack STAMP-C3 board configuration + +# Copyright 2022 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STAMP_C3 + bool "M5Stack STAMP-C3 Board" + depends on SOC_ESP32C3 diff --git a/boards/riscv/stamp_c3/Kconfig.defconfig b/boards/riscv/stamp_c3/Kconfig.defconfig new file mode 100644 index 00000000000..56e120d5d1e --- /dev/null +++ b/boards/riscv/stamp_c3/Kconfig.defconfig @@ -0,0 +1,21 @@ +# M5Stack STAMP-C3 board configuration + +# Copyright 2022 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD + default "stamp_c3" + depends on BOARD_STAMP_C3 + +config HEAP_MEM_POOL_SIZE + default 98304 if WIFI + default 16384 if BT + default 4096 + +if BT + +choice BT_HCI_BUS_TYPE + default BT_ESP32 +endchoice + +endif # BT diff --git a/boards/riscv/stamp_c3/board.cmake b/boards/riscv/stamp_c3/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/riscv/stamp_c3/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/riscv/stamp_c3/doc/index.rst b/boards/riscv/stamp_c3/doc/index.rst new file mode 100644 index 00000000000..0d3f904eb68 --- /dev/null +++ b/boards/riscv/stamp_c3/doc/index.rst @@ -0,0 +1,124 @@ +.. _stamp_c3: + +M5Stack STAMP-C3 +################## + +Overview +******** + +STAMP-C3 featuring ESPRESSIF ESP32-C3 RISC-V MCU with Wi-Fi connectivity +for IoT edge devices such as home appliances and Industrial Automation. + +For more details see the `M5Stack STAMP-C3`_ page. + +Supported Features +================== + +The STAMP-C3 board configuration supports the following hardware features: + ++-----------+------------+------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==================+ +| PMP | on-chip | arch/riscv | ++-----------+------------+------------------+ +| INTMTRX | on-chip | intc_esp32c3 | ++-----------+------------+------------------+ +| PINMUX | on-chip | pinctrl_esp32 | ++-----------+------------+------------------+ +| USB UART | on-chip | serial_esp32_usb | ++-----------+------------+------------------+ +| GPIO | on-chip | gpio_esp32 | ++-----------+------------+------------------+ +| UART | on-chip | uart_esp32 | ++-----------+------------+------------------+ +| I2C | on-chip | i2c_esp32 | ++-----------+------------+------------------+ +| SPI | on-chip | spi_esp32_spim | ++-----------+------------+------------------+ +| TWAI | on-chip | can_esp32_twai | ++-----------+------------+------------------+ + + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stamp_c3 + :goals: build + +The usual ``flash`` target will work with the ``stamp_c3`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stamp_c3 + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! stamp_c3 + +Debugging +--------- + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stamp_c3 + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stamp_c3 + :goals: debug + +References +********** + +.. target-notes:: + +.. _`M5Stack STAMP-C3`: https://docs.m5stack.com/en/core/stamp_c3 +.. _`ESP32C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _`ESP32C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/riscv/stamp_c3/stamp_c3-pinctrl.dtsi b/boards/riscv/stamp_c3/stamp_c3-pinctrl.dtsi new file mode 100644 index 00000000000..ac9f70f9f6c --- /dev/null +++ b/boards/riscv/stamp_c3/stamp_c3-pinctrl.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright 2022 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/riscv/stamp_c3/stamp_c3.dts b/boards/riscv/stamp_c3/stamp_c3.dts new file mode 100644 index 00000000000..f9f03449f9a --- /dev/null +++ b/boards/riscv/stamp_c3/stamp_c3.dts @@ -0,0 +1,150 @@ +/* + * Copyright 2022 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "stamp_c3-pinctrl.dtsi" + +/ { + model = "M5Stack STAMP-C3"; + compatible = "m5stack,stamp_c3"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + }; + + aliases { + sw0 = &button0; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + power-states { + light_sleep: light_sleep { + compatible = "zephyr,power-state"; + power-state-name = "standby"; + min-residency-us = <200>; + exit-latency-us = <60>; + }; + + deep_sleep: deep_sleep { + compatible = "zephyr,power-state"; + power-state-name = "soft-off"; + min-residency-us = <660>; + exit-latency-us = <105>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + button0: button0 { + label = "BTN"; + gpios = <&gpio0 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + }; + }; +}; + +&cpu0 { + clock-frequency = ; + cpu-power-states = <&deep_sleep &light_sleep>; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&usb_serial { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&twai { + /* requires external CAN transceiver or jumper on RX and TX pins for loopback testing */ + status = "disabled"; + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; + bus-speed = <125000>; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/riscv/stamp_c3/stamp_c3.yaml b/boards/riscv/stamp_c3/stamp_c3.yaml new file mode 100644 index 00000000000..49539b34f19 --- /dev/null +++ b/boards/riscv/stamp_c3/stamp_c3.yaml @@ -0,0 +1,16 @@ +identifier: stamp_c3 +name: M5Stack STAMP-C3 +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/riscv/stamp_c3/stamp_c3_defconfig b/boards/riscv/stamp_c3/stamp_c3_defconfig new file mode 100644 index 00000000000..56515384f21 --- /dev/null +++ b/boards/riscv/stamp_c3/stamp_c3_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BOARD_STAMP_C3=y +CONFIG_SOC_ESP32C3=y +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/riscv/stamp_c3/support/openocd.cfg b/boards/riscv/stamp_c3/support/openocd.cfg new file mode 100644 index 00000000000..5db52f70d83 --- /dev/null +++ b/boards/riscv/stamp_c3/support/openocd.cfg @@ -0,0 +1,9 @@ +# Copyright (c) 2022 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +set ESP_RTOS none + +source [find interface/esp_usb_jtag.cfg] + +source [find target/esp32c3.cfg] +adapter_khz 5000