soc: riscv32: add LiteX VexRiscV SoC

Add LiteX with softcore CPU VexRiscV SoC definitions and default
configurations.

Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>

CODEOWNERS

@@ -164,6 +164,7 @@
 /dts/arm/nxp/                             @MaureenHelm
 /dts/arm/microchip/                       @franciscomunoz @albertofloyd @scottwcpg
 /dts/riscv32/rv32m1*                      @MaureenHelm
+/dts/riscv32/riscv32-litex-vexriscv.dtsi  @mateusz-holenko @kgugala @pgielda
 /dts/bindings/                            @galak
 /dts/bindings/can/                        @alexanderwachter
 /dts/bindings/iio/adc/st*stm32-adc.yaml   @cybertale

dts/riscv32/riscv32-litex-vexriscv.dtsi

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "litex,vexriscv", "litex-dev";
+	model = "litex,vexriscv";
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			clock-frequency = <100000000>;
+			compatible = "spinalhdl,vexriscv", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			riscv,isa = "rv32imac";
+			status = "okay";
+			timebase-frequency = <32768>;
+		};
+	};
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "litex,vexriscv";
+		ranges;
+		intc0: interrupt-controller@bc0 {
+			#interrupt-cells = <2>;
+			compatible = "vexriscv,intc0";
+			interrupt-controller;
+			reg = <0xbc0 0x4 0xfc0 0x4>;
+			reg-names = "irq_mask", "irq_pending";
+			riscv,max-priority = <7>;
+			riscv,ndev = <52>;
+		};
+		uart0: serial@e0001800 {
+			compatible = "litex,uart0";
+			interrupt-parent = <&intc0>;
+			interrupts = <2 10>;
+			reg = <0xe0001800 0x18>;
+			reg-names = "control";
+			label = "uart0";
+			status = "disabled";
+		};
+		timer0: serial@e0002800 {
+			compatible = "litex,timer0";
+			interrupt-parent = <&intc0>;
+			interrupts = <1 0>;
+			reg = <0xe0002800 0x40>;
+			reg-names = "control";
+			label = "timer0";
+			status = "disabled";
+		};
+	};
+};

soc/riscv32/litex-vexriscv/CMakeLists.txt

@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_sources(
+    ../riscv-privilege/common/soc_irq.S
+    ../riscv-privilege/common/vector.S
+)

soc/riscv32/litex-vexriscv/Kconfig.defconfig

@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_RISCV32_LITEX_VEXRISCV
+
+config SOC
+	string
+	default "litex-vexriscv"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 100000000
+
+config RISCV_HAS_CPU_IDLE
+	bool
+
+config RISCV_HAS_PLIC
+	bool
+
+config NUM_IRQS
+	int
+	default 12
+
+endif # SOC_RISCV32_LITEX_VEXRISCV

soc/riscv32/litex-vexriscv/Kconfig.soc

@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_RISCV32_LITEX_VEXRISCV
+	bool "LiteX VexRiscv system implementation"
+	select ATOMIC_OPERATIONS_C

soc/riscv32/litex-vexriscv/linker.ld

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/riscv32/common/linker.ld>

soc/riscv32/litex-vexriscv/soc.h

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __RISCV32_LITEX_VEXRISCV_SOC_H_
+#define __RISCV32_LITEX_VEXRISCV_SOC_H_
+
+#include "../riscv-privilege/common/soc_common.h"
+#include <generated_dts_board.h>
+
+/* lib-c hooks required RAM defined variables */
+#define RISCV_RAM_BASE              DT_MMIO_SRAM_0_BASE_ADDRESS
+#define RISCV_RAM_SIZE              DT_MMIO_SRAM_0_SIZE
+
+#endif /* __RISCV32_LITEX_VEXRISCV_SOC_H_ */