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doc: eSPI: Update link to eSPI spec

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Add link to eSPI spec 1.5
Update coding guidelines for eSPI bus

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
This commit is contained in:
Jose Alberto Meza 2024-02-22 10:04:49 -08:00 • committed by Anas Nashif
commit 33f905009d
2 changed files with 5 additions and 4 deletions
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5
doc/contribute/coding_guidelines/index.rst
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@ -1212,8 +1212,8 @@ Related GitHub Issues and Pull Requests are tagged with the `Inclusive Language
- -
* - eSPI * - eSPI
- * ``master / slave`` => TBD - * ``master / slave`` => ``controller / target``
- - Refer to `eSPI Specification`_ for new terminology
* - gPTP * - gPTP
- * ``master / slave`` => TBD - * ``master / slave`` => TBD
@ -1254,6 +1254,7 @@ Related GitHub Issues and Pull Requests are tagged with the `Inclusive Language
.. _OSHWA Resolution to Redefine SPI Signal Names: https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/ .. _OSHWA Resolution to Redefine SPI Signal Names: https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/
.. _CAN in Automation Inclusive Language news post: https://www.can-cia.org/news/archive/view/?tx_news_pi1%5Bnews%5D=699&tx_news_pi1%5Bday%5D=6&tx_news_pi1%5Bmonth%5D=12&tx_news_pi1%5Byear%5D=2020&cHash=784e79eb438141179386cf7c29ed9438 .. _CAN in Automation Inclusive Language news post: https://www.can-cia.org/news/archive/view/?tx_news_pi1%5Bnews%5D=699&tx_news_pi1%5Bday%5D=6&tx_news_pi1%5Bmonth%5D=12&tx_news_pi1%5Byear%5D=2020&cHash=784e79eb438141179386cf7c29ed9438
.. _CAN in Automation Inclusive Language: https://can-newsletter.org/canopen/categories/ .. _CAN in Automation Inclusive Language: https://can-newsletter.org/canopen/categories/
.. _eSPI Specification: https://downloadmirror.intel.com/27055/327432%20espi_base_specification%20R1-5.pdf
Rule A.3: Macro name collisions Rule A.3: Macro name collisions

4
doc/hardware/peripherals/espi.rst
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@ -8,7 +8,7 @@ Overview
The eSPI (enhanced serial peripheral interface) is a serial bus that is The eSPI (enhanced serial peripheral interface) is a serial bus that is
based on SPI. It also features a four-wire interface (receive, transmit, clock based on SPI. It also features a four-wire interface (receive, transmit, clock
and slave select) and three configurations: single IO, dual IO and quad IO. and target select) and three configurations: single IO, dual IO and quad IO.
The technical advancements include lower voltage signal levels (1.8V vs. 3.3V), The technical advancements include lower voltage signal levels (1.8V vs. 3.3V),
lower pin count, and the frequency is twice as fast (66MHz vs. 33MHz) lower pin count, and the frequency is twice as fast (66MHz vs. 33MHz)
@ -24,4 +24,4 @@ API Reference
.. doxygengroup:: espi_interface .. doxygengroup:: espi_interface
.. _eSPI interface specification: .. _eSPI interface specification:
https://www.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0_cb.pdf https://downloadmirror.intel.com/27055/327432%20espi_base_specification%20R1-5.pdf