From 33d9487efcb5b7bc8f726d17c41d1256df5a4d91 Mon Sep 17 00:00:00 2001 From: Nhut Nguyen Date: Mon, 3 Mar 2025 07:36:40 +0000 Subject: [PATCH] drivers: pinctrl: Add support for RZ/A3UL This is the initial commit to support pinctrl driver for Renesas RZ/A3UL Signed-off-by: Nhut Nguyen Signed-off-by: Phuc Pham --- .../rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi | 18 +++ drivers/pinctrl/renesas/rz/Kconfig | 3 +- dts/arm64/renesas/rz/rza/r9a07g063.dtsi | 6 + dts/bindings/pinctrl/renesas,rza-pinctrl.yaml | 105 +++++++++++++++++ .../pinctrl/renesas/pinctrl-rza-common.h | 108 ++++++++++++++++++ soc/renesas/rz/common/pinctrl_rza.h | 105 +++++++++++++++++ soc/renesas/rz/rza3ul/pinctrl_soc.h | 11 ++ 7 files changed, 355 insertions(+), 1 deletion(-) create mode 100644 boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi create mode 100644 dts/bindings/pinctrl/renesas,rza-pinctrl.yaml create mode 100644 include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza-common.h create mode 100644 soc/renesas/rz/common/pinctrl_rza.h create mode 100644 soc/renesas/rz/rza3ul/pinctrl_soc.h diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi b/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi new file mode 100644 index 00000000000..25e26032f61 --- /dev/null +++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&pinctrl { + /omit-if-no-ref/ scif0_pins: scif0 { + scif0-pinmux { + pinmux = , /* RXD */ + ; /* TXD */ + drive-strength = <1>; + slew-rate = "fast"; + }; + }; +}; diff --git a/drivers/pinctrl/renesas/rz/Kconfig b/drivers/pinctrl/renesas/rz/Kconfig index 3b5f62709a7..f43b898948f 100644 --- a/drivers/pinctrl/renesas/rz/Kconfig +++ b/drivers/pinctrl/renesas/rz/Kconfig @@ -14,7 +14,8 @@ config PINCTRL_RENESAS_RZ default y depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED \ || DT_HAS_RENESAS_RZN_PINCTRL_ENABLED \ - || DT_HAS_RENESAS_RZT_PINCTRL_ENABLED + || DT_HAS_RENESAS_RZT_PINCTRL_ENABLED \ + || DT_HAS_RENESAS_RZA_PINCTRL_ENABLED select USE_RZ_FSP_IOPORT help Enable Renesas RZ pinctrl driver. diff --git a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi index 6b766feb22a..3fa7f96707d 100644 --- a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi +++ b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi @@ -47,5 +47,11 @@ #interrupt-cells = <4>; status = "okay"; }; + + pinctrl: pin-controller@11030000 { + compatible = "renesas,rza-pinctrl"; + reg = <0x11030000 DT_SIZE_K(64)>; + reg-names = "pinctrl"; + }; }; }; diff --git a/dts/bindings/pinctrl/renesas,rza-pinctrl.yaml b/dts/bindings/pinctrl/renesas,rza-pinctrl.yaml new file mode 100644 index 00000000000..7b2da83da1f --- /dev/null +++ b/dts/bindings/pinctrl/renesas,rza-pinctrl.yaml @@ -0,0 +1,105 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: | + Below generic example shows of supported pinctrl definitions: + + #include + example_pins: device_pin { + device-pinmux { + pinmux = , + ; + bias_pull_up; + renesas,filter = RZA_FILTER_SET(RZA_FILNUM_8_STAGE,RZA_FILCLKSEL_DIV_18000); + drive-strength = <1>; + slew-rate = "fast"; + }; + + device-spins { + pins = , ; + input-enable; + renesas,filter = RZA_FILTER_SET(RZA_FILNUM_8_STAGE,RZA_FILCLKSEL_DIV_18000); + drive-strength = <2>; + slew-rate = "fast"; + }; + }; + + +compatible: renesas,rza-pinctrl + +include: base.yaml +properties: + reg: + required: true + + reg-names: + required: true + +child-binding: + description: | + This RZA pins mux/cfg nodes description. + + child-binding: + description: | + The RZA pinmux/pincfg configuration nodes description. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-high-impedance + - bias-pull-down + - bias-pull-up + - bias-pull-pin-default + - drive-strength + - input-enable + - input-disable + - output-enable + - power-source + - low-power-enable + - low-power-disable + + properties: + pinmux: + type: array + description: | + Pinmux configuration node. + Values are constructed from GPIO port number, pin number, and + alternate function configuration number using the RZA_PINMUX() + helper macro in pinctrl_rza.h + + pins: + type: array + description: | + Special Purpose pins configuration node. + Values are define in pinctrl_rza.h. + Ex: BSP_IO_XSPI_IO0,BSP_IO_I3C_SCL,... + + drive-strength: + type: int + default: 0 + description: | + Maximum sink or source current in mA for pin which shall be selected + depending on device and pin group. + + renesas,filter: + type: int + default: 0 + description: | + Digital Noise Filter configuration for a pin which shall be defined + using RZA_FILTER_SET() helper macro in pinctrl_rza.h to specify + FILNUM and FILCLKSEL. With 24Mhz external clock: + - min debounce time will be 166.666ns for FILNUM=0 and FILCLKSEL=0 + - max debounce time will be 24ms for FILNUM=3 and FILCLKSEL=3. + This property intentionally redefined to avoid unnecessary conversation from usec to + FILNUM and FILCLKSEL values depending on external clock value as this configuration + is static. + + slew-rate: + type: string + default: "fast" + enum: + - "slow" + - "fast" + description: | + Select slew rate for pin. diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza-common.h new file mode 100644 index 00000000000..38bf44752f9 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza-common.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA_COMMON_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA_COMMON_H_ + +/* Superset list of all possible IO ports. */ +#define PORT_00 0x0000 /* IO port 0 */ +#define PORT_01 0x0100 /* IO port 1 */ +#define PORT_02 0x0200 /* IO port 2 */ +#define PORT_03 0x0300 /* IO port 3 */ +#define PORT_04 0x0400 /* IO port 4 */ +#define PORT_05 0x0500 /* IO port 5 */ +#define PORT_06 0x0600 /* IO port 6 */ +#define PORT_07 0x0700 /* IO port 7 */ +#define PORT_08 0x0800 /* IO port 8 */ +#define PORT_09 0x0900 /* IO port 9 */ +#define PORT_10 0x0A00 /* IO port 10 */ +#define PORT_11 0x0B00 /* IO port 11 */ +#define PORT_12 0x0C00 /* IO port 12 */ +#define PORT_13 0x0D00 /* IO port 13 */ +#define PORT_14 0x0E00 /* IO port 14 */ +#define PORT_15 0x0F00 /* IO port 15 */ +#define PORT_16 0x1000 /* IO port 16 */ +#define PORT_17 0x1100 /* IO port 17 */ +#define PORT_18 0x1200 /* IO port 18 */ + +/* + * Create the value contain port/pin/function information + * + * port: port number BSP_IO_PORT_00..BSP_IO_PORT_18 + * pin: pin number + * func: pin function + */ +#define RZA_PINMUX(port, pin, func) (port | pin | (func << 4)) + +/* Special purpose port */ +#define BSP_IO_NMI 0xFFFF0100 /* NMI */ + +#define BSP_IO_TMS_SWDIO 0xFFFF0200 /* TMS_SWDIO */ + +#define BSP_IO_TDO 0xFFFF0300 /* TDO */ + +#define BSP_IO_AUDIO_CLK1 0xFFFF0400 /* AUDIO_CLK1 */ +#define BSP_IO_AUDIO_CLK2 0xFFFF0401 /* AUDIO_CLK2 */ + +#define BSP_IO_SD0_CLK 0xFFFF0600 /* CD0_CLK */ +#define BSP_IO_SD0_CMD 0xFFFF0601 /* CD0_CMD */ +#define BSP_IO_SD0_RST_N 0xFFFF0602 /* CD0_RST_N */ + +#define BSP_IO_SD0_DATA0 0xFFFF0700 /* SD0_DATA0 */ +#define BSP_IO_SD0_DATA1 0xFFFF0701 /* SD0_DATA1 */ +#define BSP_IO_SD0_DATA2 0xFFFF0702 /* SD0_DATA2 */ +#define BSP_IO_SD0_DATA3 0xFFFF0703 /* SD0_DATA3 */ +#define BSP_IO_SD0_DATA4 0xFFFF0704 /* SD0_DATA4 */ +#define BSP_IO_SD0_DATA5 0xFFFF0705 /* SD0_DATA5 */ +#define BSP_IO_SD0_DATA6 0xFFFF0706 /* SD0_DATA6 */ +#define BSP_IO_SD0_DATA7 0xFFFF0707 /* SD0_DATA7 */ + +#define BSP_IO_SD1_CLK 0xFFFF0800 /* SD1_CLK */ +#define BSP_IO_SD1_CMD 0xFFFF0801 /* SD1_CMD */ + +#define BSP_IO_SD1_DATA0 0xFFFF0900 /* SD1_DATA0 */ +#define BSP_IO_SD1_DATA1 0xFFFF0901 /* SD1_DATA1 */ +#define BSP_IO_SD1_DATA2 0xFFFF0902 /* SD1_DATA2 */ +#define BSP_IO_SD1_DATA3 0xFFFF0903 /* SD1_DATA3 */ + +#define BSP_IO_QSPI0_SPCLK 0xFFFF0A00 /* QSPI0_SPCLK */ +#define BSP_IO_QSPI0_IO0 0xFFFF0A01 /* QSPI0_IO0 */ +#define BSP_IO_QSPI0_IO1 0xFFFF0A02 /* QSPI0_IO1 */ +#define BSP_IO_QSPI0_IO2 0xFFFF0A03 /* QSPI0_IO2 */ +#define BSP_IO_QSPI0_IO3 0xFFFF0A04 /* QSPI0_IO3 */ +#define BSP_IO_QSPI0_SSL 0xFFFF0A05 /* QSPI0_SSL */ + +#define BSP_IO_OM_CS1_N 0xFFFF0B00 /* OM_CS1_N */ +#define BSP_IO_OM_DQS 0xFFFF0B01 /* OM_DQS */ +#define BSP_IO_OM_SIO4 0xFFFF0B02 /* OM_SIO4 */ +#define BSP_IO_OM_SIO5 0xFFFF0B03 /* OM_SIO5 */ +#define BSP_IO_OM_SIO6 0xFFFF0B04 /* OM_SIO6 */ +#define BSP_IO_OM_SIO7 0xFFFF0B05 /* OM_SIO7 */ + +#define BSP_IO_QSPI_RESET_N 0xFFFF0C00 /* QSPI_RESET_N */ +#define BSP_IO_QSPI_WP_N 0xFFFF0C01 /* QSPI_WP_N */ + +#define BSP_IO_WDTOVF_PERROUT_N 0xFFFF0D00 /* WDTOVF_PERROUT_N */ + +#define BSP_IO_RIIC0_SDA 0xFFFF0E00 /* RIIC0_SDA */ +#define BSP_IO_RIIC0_SCL 0xFFFF0E01 /* RIIC0_SCL */ +#define BSP_IO_RIIC1_SDA 0xFFFF0E02 /* RIIC1_SDA */ +#define BSP_IO_RIIC1_SCL 0xFFFF0E03 /* RIIC1_SCL */ + +/* FILNUM */ +#define RZA_FILNUM_4_STAGE 0 +#define RZA_FILNUM_8_STAGE 1 +#define RZA_FILNUM_12_STAGE 2 +#define RZA_FILNUM_16_STAGE 3 + +/* FILCLKSEL */ +#define RZA_FILCLKSEL_NOT_DIV 0 +#define RZA_FILCLKSEL_DIV_9000 1 +#define RZA_FILCLKSEL_DIV_18000 2 +#define RZA_FILCLKSEL_DIV_36000 3 + +#define RZA_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA_COMMON_H_ */ diff --git a/soc/renesas/rz/common/pinctrl_rza.h b/soc/renesas/rz/common/pinctrl_rza.h new file mode 100644 index 00000000000..5471a358699 --- /dev/null +++ b/soc/renesas/rz/common/pinctrl_rza.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZA_H_ +#define ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZA_H_ + +#include +#include +#include +#include "r_ioport.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Porting */ +typedef struct pinctrl_cfg_data_t { + uint32_t reserved: 4; + uint32_t pupd_reg: 6; + uint32_t iolh_reg: 6; + uint32_t pmc_reg: 1; + uint32_t sr_reg: 1; + uint32_t ien_reg: 1; + uint32_t filonoff_reg: 1; + uint32_t filnum_reg: 2; + uint32_t filclksel_reg: 2; + uint32_t pfc_reg: 3; +} pinctrl_cfg_data_t; + +typedef struct pinctrl_soc_pin_t { + bsp_io_port_pin_t port_pin; + pinctrl_cfg_data_t config; +} pinctrl_soc_pin_t; + +/* Iterate over each pinctrl-n phandle child */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \ + DT_FOREACH_CHILD(DT_PHANDLE_BY_IDX(node_id, state_prop, idx), \ + Z_PINCTRL_STATE_PIN_CHILD_INIT) + +/* Iterate over each pinctrl-n phandle child */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_PROP_ELEM_SEP(node_id, prop, Z_PINCTRL_STATE_PIN_INIT, ())}; + +#define Z_PINCTRL_STATE_PIN_CHILD_INIT(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, pinmux), \ + (DT_FOREACH_PROP_ELEM(node_id, pinmux, Z_PINCTRL_PINMUX_INIT)), \ + ()) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, pins), \ + (DT_FOREACH_PROP_ELEM(node_id, pins, Z_PINCTRL_SPECIAL_PINS_INIT)), \ + ()) + +#define RZA_GET_PORT_PIN(pinmux) (pinmux & ~(0xF << 4)) +#define RZA_GET_FUNC(pinmux) ((pinmux & 0xF0) >> 4) + +#define RZA_GET_PU_PD(node_id) \ + DT_PROP(node_id, bias_pull_up) == 1 ? 1U : (DT_PROP(node_id, bias_pull_down) == 1 ? 2U : 0U) + +#define RZA_GET_FILNUM(node_id) ((DT_PROP(node_id, renesas_filter) >> 2) & 0x3) + +#define RZA_GET_FILCLKSEL(node_id) (DT_PROP(node_id, renesas_filter) & 0x3) + +#define RZA_FILTER_ON_OFF(node_id) COND_CODE_0(DT_PROP(node_id, renesas_filter), (0), (1)) + +/* Process pinmux cfg */ +#define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx) \ + { \ + .port_pin = RZA_GET_PORT_PIN(DT_PROP_BY_IDX(node_id, state_prop, idx)), \ + .config = \ + { \ + .reserved = 0, \ + .pupd_reg = RZA_GET_PU_PD(node_id), \ + .iolh_reg = DT_PROP(node_id, drive_strength), \ + .pmc_reg = 1, \ + .sr_reg = DT_ENUM_IDX(node_id, slew_rate), \ + .ien_reg = DT_PROP(node_id, input_enable), \ + .filonoff_reg = RZA_FILTER_ON_OFF(node_id), \ + .filnum_reg = RZA_GET_FILNUM(node_id), \ + .filclksel_reg = RZA_GET_FILCLKSEL(node_id), \ + .pfc_reg = RZA_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)), \ + }, \ + }, + +#define Z_PINCTRL_SPECIAL_PINS_INIT(node_id, state_prop, idx) \ + { \ + .port_pin = DT_PROP_BY_IDX(node_id, state_prop, idx), \ + .config = \ + { \ + .reserved = 0, \ + .pupd_reg = RZA_GET_PU_PD(node_id), \ + .iolh_reg = DT_PROP(node_id, drive_strength), \ + .pmc_reg = 0, \ + .sr_reg = DT_ENUM_IDX(node_id, slew_rate), \ + .ien_reg = DT_PROP(node_id, input_enable), \ + .filonoff_reg = RZA_FILTER_ON_OFF(node_id), \ + .filnum_reg = RZA_GET_FILNUM(node_id), \ + .filclksel_reg = RZA_GET_FILCLKSEL(node_id), \ + .pfc_reg = 0, \ + }, \ + }, + +#ifdef __cplusplus +} +#endif +#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZA_H_ */ diff --git a/soc/renesas/rz/rza3ul/pinctrl_soc.h b/soc/renesas/rz/rza3ul/pinctrl_soc.h new file mode 100644 index 00000000000..44733d79afd --- /dev/null +++ b/soc/renesas/rz/rza3ul/pinctrl_soc.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZ_RZA3UL_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZ_RZA3UL_PINCTRL_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZ_RZA3UL_PINCTRL_SOC_H_ */