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linker: arm: Fix cortex_m dtcm and ccm sections to work with relocation

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Adds missing DTCM_ADDR and CCM_ADDR macros needed by the linker script
generated by scripts/gen_relocate_app.py.

Moves associated bss_end, noinit_end, and data_end linker symbols to
account for section relocation. Without this change, the section sizes
calculated in z_bss_zero() and z_data_copy() are incorrect.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm 2021-01-04 18:29:32 -06:00 • committed by Ioannis Glaropoulos
commit 334014a8fe
2 changed files with 18 additions and 12 deletions
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22
include/arch/arm/aarch32/cortex_m/scripts/linker.ld
View file

@ -66,6 +66,16 @@
#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#endif
#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ccm), okay)
#define CCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ccm))
#define CCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ccm))
#endif
#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
#define DTCM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm))
#define DTCM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm))
#endif
#if defined(CONFIG_CUSTOM_SECTION_ALIGN)
_region_min_align = CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE;
#else
@ -96,10 +106,10 @@ MEMORY
FLASH_CCFG (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE
#endif
#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ccm), okay)
CCM (rw) : ORIGIN = DT_REG_ADDR(DT_CHOSEN(zephyr_ccm)), LENGTH = DT_REG_SIZE(DT_CHOSEN(zephyr_ccm))
CCM (rw) : ORIGIN = CCM_ADDR, LENGTH = CCM_SIZE
#endif
#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
DTCM (rw) : ORIGIN = DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm)), LENGTH = DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm))
DTCM (rw) : ORIGIN = DTCM_ADDR, LENGTH = DTCM_SIZE
#endif
SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
#ifdef CONFIG_BT_STM32_IPM
@ -418,27 +428,25 @@ GROUP_START(DTCM)
__dtcm_bss_start = .;
*(.dtcm_bss)
*(".dtcm_bss.*")
__dtcm_bss_end = .;
} GROUP_LINK_IN(DTCM)
__dtcm_bss_end = .;
SECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))
{
__dtcm_noinit_start = .;
*(.dtcm_noinit)
*(".dtcm_noinit.*")
__dtcm_noinit_end = .;
} GROUP_LINK_IN(DTCM)
__dtcm_noinit_end = .;
SECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(4))
{
__dtcm_data_start = .;
*(.dtcm_data)
*(".dtcm_data.*")
__dtcm_data_end = .;
} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)
__dtcm_data_end = .;
__dtcm_end = .;
__dtcm_data_rom_start = LOADADDR(_DTCM_DATA_SECTION_NAME);

8
soc/arm/st_stm32/common/ccm.ld
View file

@ -8,27 +8,25 @@ GROUP_START(CCM)
__ccm_bss_start = .;
*(.ccm_bss)
*(".ccm_bss.*")
__ccm_bss_end = .;
} GROUP_LINK_IN(CCM)
__ccm_bss_end = .;
SECTION_PROLOGUE(_CCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(4))
{
__ccm_noinit_start = .;
*(.ccm_noinit)
*(".ccm_noinit.*")
__ccm_noinit_end = .;
} GROUP_LINK_IN(CCM)
__ccm_noinit_end = .;
SECTION_PROLOGUE(_CCM_DATA_SECTION_NAME,,SUBALIGN(4))
{
__ccm_data_start = .;
*(.ccm_data)
*(".ccm_data.*")
__ccm_data_end = .;
} GROUP_LINK_IN(CCM AT> ROMABLE_REGION)
__ccm_data_end = .;
__ccm_end = .;
__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);