boards: riscv: hifive1: add openocd configuration

Add configurations flashing and debugging for openocd.
The change makes `west debug` and `west flash` use the setting defaultly.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>

boards/riscv/hifive1/board.cmake

@@ -11,6 +11,11 @@ set(QEMU_FLAGS_${ARCH}
   -machine sifive_e
   )
 
-board_set_debugger_ifnset(qemu)
 board_set_flasher_ifnset(hifive1)
 board_finalize_runner_args(hifive1)
+
+board_runner_args(openocd --cmd-load "hifive1-load")
+board_runner_args(openocd --cmd-reset-halt "hifive1-reset-halt")
+board_runner_args(openocd --cmd-post-verify "hifive1-post-verify")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/riscv/hifive1/hifive1_defconfig

@@ -10,3 +10,4 @@ CONFIG_UART_CONSOLE=y
 CONFIG_PINCTRL=y
 CONFIG_GPIO=y
 CONFIG_QEMU_ICOUNT_SHIFT=6
+CONFIG_BUILD_OUTPUT_HEX=y

boards/riscv/hifive1/support/openocd.cfg

@@ -1,7 +1,39 @@
-source [find board/sifive-hifive1.cfg]
+adapter speed  10000
+adapter driver ftdi
+
+ftdi device_desc "Dual RS232-HS"
+ftdi vid_pid 0x0403 0x6010
+ftdi layout_init 0x0008 0x000b
+ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+
+proc hifive1-load {file} {
+        flash protect 0 64 last off
+        flash write_image erase $file
+}
+
+proc hifive1-reset-halt {} {
+	halt
+}
+
+proc hifive1-post-verify {} {
+	# `reset halt` not correctly works.
+	# toggles the nSRST directly.
+	ftdi set_signal nSRST 0
+	ftdi set_signal nSRST z
+	shutdown
+}
 
 $_TARGETNAME configure -event gdb-attach {
-        reset halt
+        halt
         gdb_breakpoint_override hard
 }