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boards: nucleo_wl55jc: Use dts for clocks configuration

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Convert board to use of device tree for clocks configuration.

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This commit is contained in:
Alexandre Bourdiol 2021-04-28 18:51:28 +02:00 • committed by Anas Nashif
commit 31a02a1068
2 changed files with 24 additions and 20 deletions
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23
boards/arm/nucleo_wl55jc/nucleo_wl55jc.dts
View file

@ -61,6 +61,29 @@
};
};
&clk_hsi {
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <6>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
cpu1-prescaler = <1>;
cpu2-prescaler = <1>;
ahb3-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&lpuart1 {
pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
current-speed = <115200>;

21
boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig
View file

@ -1,7 +1,5 @@
CONFIG_SOC_SERIES_STM32WLX=y
CONFIG_SOC_STM32WL55XX=y
# 48MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
# enable uart driver
CONFIG_SERIAL=y
@ -12,25 +10,8 @@ CONFIG_PINMUX=y
# enable GPIO
CONFIG_GPIO=y
# clock configuration
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSI as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
# HSE is present on nucleo board (32MHz), but reserved for further LoRa use
# CONFIG_CLOCK_STM32_HSE_CLOCK=32000000
# produce 80MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=6
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
CONFIG_CLOCK_STM32_CPU1_PRESCALER=1
CONFIG_CLOCK_STM32_CPU2_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=1
CONFIG_CLOCK_STM32_APB2_PRESCALER=1
CONFIG_CLOCK_STM32_AHB3_PRESCALER=1
# console
CONFIG_CONSOLE=y