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soc: st: common: Rename STM32_PWR_WKUP_PIN_SRC_x

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This renames the STM32_PWR_WKUP_PIN_SRC_x symbols to better match
their meaning. It also adds a new symbol (STM32_PWR_WKUP_PIN_NOT_MUXED)
for SoCs without wake-up mux support.

Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
This commit is contained in:
Tomáš Juřena 2025-04-09 11:54:52 +02:00 • committed by Benjamin Cabé
commit 315ea56fef
9 changed files with 56 additions and 55 deletions
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12
dts/arm/st/c0/stm32c0.dtsi
View file

@ -11,13 +11,13 @@
* *
* &pwr { * &pwr {
* wkup-pin@2 { * wkup-pin@2 {
* wkup-gpios = <&gpioX YY STM32_PWR_WKUP_PIN_SRC_0>; * wkup-gpios = <&gpioX YY STM32_PWR_WKUP_PIN_NOT_MUXED>;
* }; * };
* wkup-pin@5 { * wkup-pin@5 {
* wkup-gpios = <&gpioX YY STM32_PWR_WKUP_PIN_SRC_0>; * wkup-gpios = <&gpioX YY STM32_PWR_WKUP_PIN_NOT_MUXED>;
* }; * };
* wkup-pin@6 { * wkup-pin@6 {
* wkup-gpios = <&gpioX YY STM32_PWR_WKUP_PIN_SRC_0>; * wkup-gpios = <&gpioX YY STM32_PWR_WKUP_PIN_NOT_MUXED>;
* }; * };
* }; * };
* *
@ -229,7 +229,7 @@
wkup-pin@1 { wkup-pin@1 {
reg = <0x1>; reg = <0x1>;
wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
wkup-pin@2 { wkup-pin@2 {
@ -238,12 +238,12 @@
wkup-pin@3 { wkup-pin@3 {
reg = <0x3>; reg = <0x3>;
wkup-gpios = <&gpiob 6 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpiob 6 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
wkup-pin@4 { wkup-pin@4 {
reg = <0x4>; reg = <0x4>;
wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
wkup-pin@5 { wkup-pin@5 {

10
dts/arm/st/l4/stm32l4r5Xi.dtsi
View file

@ -20,22 +20,22 @@
&pwr { &pwr {
wkup-pin@1 { wkup-pin@1 {
wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
wkup-pin@2 { wkup-pin@2 {
wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
wkup-pin@3 { wkup-pin@3 {
wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
wkup-pin@4 { wkup-pin@4 {
wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
wkup-pin@5 { wkup-pin@5 {
wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
}; };

48
dts/arm/st/u5/stm32u5.dtsi
View file

@ -876,58 +876,58 @@
wkup-pin@1 { wkup-pin@1 {
reg = <0x1>; reg = <0x1>;
wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>, wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_EVT_SRC_0>,
<&gpiob 2 STM32_PWR_WKUP_PIN_SRC_1>, <&gpiob 2 STM32_PWR_WKUP_EVT_SRC_1>,
<&gpioe 4 STM32_PWR_WKUP_PIN_SRC_2>; <&gpioe 4 STM32_PWR_WKUP_EVT_SRC_2>;
}; };
wkup-pin@2 { wkup-pin@2 {
reg = <0x2>; reg = <0x2>;
wkup-gpios = <&gpioa 4 STM32_PWR_WKUP_PIN_SRC_0>, wkup-gpios = <&gpioa 4 STM32_PWR_WKUP_EVT_SRC_0>,
<&gpioc 13 STM32_PWR_WKUP_PIN_SRC_1>, <&gpioc 13 STM32_PWR_WKUP_EVT_SRC_1>,
<&gpioe 5 STM32_PWR_WKUP_PIN_SRC_2>; <&gpioe 5 STM32_PWR_WKUP_EVT_SRC_2>;
}; };
wkup-pin@3 { wkup-pin@3 {
reg = <0x3>; reg = <0x3>;
wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_PIN_SRC_0>, wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_EVT_SRC_0>,
<&gpioa 1 STM32_PWR_WKUP_PIN_SRC_1>, <&gpioa 1 STM32_PWR_WKUP_EVT_SRC_1>,
<&gpiob 6 STM32_PWR_WKUP_PIN_SRC_2>; <&gpiob 6 STM32_PWR_WKUP_EVT_SRC_2>;
}; };
wkup-pin@4 { wkup-pin@4 {
reg = <0x4>; reg = <0x4>;
wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>, wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_EVT_SRC_0>,
<&gpiob 1 STM32_PWR_WKUP_PIN_SRC_1>, <&gpiob 1 STM32_PWR_WKUP_EVT_SRC_1>,
<&gpiob 7 STM32_PWR_WKUP_PIN_SRC_2>; <&gpiob 7 STM32_PWR_WKUP_EVT_SRC_2>;
}; };
wkup-pin@5 { wkup-pin@5 {
reg = <0x5>; reg = <0x5>;
wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_SRC_0>, wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_EVT_SRC_0>,
<&gpioa 3 STM32_PWR_WKUP_PIN_SRC_1>, <&gpioa 3 STM32_PWR_WKUP_EVT_SRC_1>,
<&gpiob 8 STM32_PWR_WKUP_PIN_SRC_2>; <&gpiob 8 STM32_PWR_WKUP_EVT_SRC_2>;
}; };
wkup-pin@6 { wkup-pin@6 {
reg = <0x6>; reg = <0x6>;
wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_PIN_SRC_0>, wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_EVT_SRC_0>,
<&gpioa 5 STM32_PWR_WKUP_PIN_SRC_1>, <&gpioa 5 STM32_PWR_WKUP_EVT_SRC_1>,
<&gpioe 7 STM32_PWR_WKUP_PIN_SRC_2>; <&gpioe 7 STM32_PWR_WKUP_EVT_SRC_2>;
}; };
wkup-pin@7 { wkup-pin@7 {
reg = <0x7>; reg = <0x7>;
wkup-gpios = <&gpiob 15 STM32_PWR_WKUP_PIN_SRC_0>, wkup-gpios = <&gpiob 15 STM32_PWR_WKUP_EVT_SRC_0>,
<&gpioa 6 STM32_PWR_WKUP_PIN_SRC_1>, <&gpioa 6 STM32_PWR_WKUP_EVT_SRC_1>,
<&gpioe 8 STM32_PWR_WKUP_PIN_SRC_2>; <&gpioe 8 STM32_PWR_WKUP_EVT_SRC_2>;
}; };
wkup-pin@8 { wkup-pin@8 {
reg = <0x8>; reg = <0x8>;
wkup-gpios = <&gpiof 2 STM32_PWR_WKUP_PIN_SRC_0>, wkup-gpios = <&gpiof 2 STM32_PWR_WKUP_EVT_SRC_0>,
<&gpioa 7 STM32_PWR_WKUP_PIN_SRC_1>, <&gpioa 7 STM32_PWR_WKUP_EVT_SRC_1>,
<&gpiob 10 STM32_PWR_WKUP_PIN_SRC_2>; <&gpiob 10 STM32_PWR_WKUP_EVT_SRC_2>;
}; };
}; };

4
dts/arm/st/wb/stm32wb.dtsi
View file

@ -535,12 +535,12 @@
wkup-pin@1 { wkup-pin@1 {
reg = <0x1>; reg = <0x1>;
wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
wkup-pin@4 { wkup-pin@4 {
reg = <0x4>; reg = <0x4>;
wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
}; };
}; };

6
dts/arm/st/wb/stm32wb55Xg.dtsi
View file

@ -24,16 +24,16 @@
&pwr { &pwr {
wkup-pin@2 { wkup-pin@2 {
reg = <0x2>; reg = <0x2>;
wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
wkup-pin@3 { wkup-pin@3 {
reg = <0x3>; reg = <0x3>;
wkup-gpios = <&gpioc 12 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioc 12 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
wkup-pin@5 { wkup-pin@5 {
reg = <0x5>; reg = <0x5>;
wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
}; };

6
dts/arm/st/wl/stm32wl.dtsi
View file

@ -523,17 +523,17 @@
wkup-pin@1 { wkup-pin@1 {
reg = <0x1>; reg = <0x1>;
wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
wkup-pin@2 { wkup-pin@2 {
reg = <0x2>; reg = <0x2>;
wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
wkup-pin@3 { wkup-pin@3 {
reg = <0x3>; reg = <0x3>;
wkup-gpios = <&gpiob 3 STM32_PWR_WKUP_PIN_SRC_0>; wkup-gpios = <&gpiob 3 STM32_PWR_WKUP_PIN_NOT_MUXED>;
}; };
}; };
}; };

6
dts/bindings/power/st,stm32-pwr.yaml
View file

@ -62,6 +62,6 @@ child-binding:
description: | description: |
Specifies the GPIOs, if any, that are associated with the wake-up pin. Specifies the GPIOs, if any, that are associated with the wake-up pin.
For example, for GPIO B2 associated with wakeup source 1 on wake-up For example, for GPIO PB2 associated with wakeup source 1 on wake-up
pin 1 on STM32U5 SoCs: event 1 on STM32U5 SoCs:
wkup-gpios = <&gpiob 2 STM32_PWR_WKUP_PIN_SRC_1>, <...>; wkup-gpios = <&gpiob 2 STM32_PWR_WKUP_EVT_SRC_1>, <...>;

7
include/zephyr/dt-bindings/power/stm32_pwr.h
View file

@ -17,9 +17,10 @@
* @{ * @{
*/ */
#define STM32_PWR_WKUP_PIN_SRC_0 0 #define STM32_PWR_WKUP_PIN_NOT_MUXED STM32_PWR_WKUP_EVT_SRC_0
#define STM32_PWR_WKUP_PIN_SRC_1 1 #define STM32_PWR_WKUP_EVT_SRC_0 0
#define STM32_PWR_WKUP_PIN_SRC_2 (1 << 2) #define STM32_PWR_WKUP_EVT_SRC_1 1
#define STM32_PWR_WKUP_EVT_SRC_2 (1 << 2)
/** @} */ /** @} */

12
soc/st/stm32/common/stm32_wkup_pins.c
View file

@ -225,11 +225,11 @@ static void wkup_pin_setup(const struct wkup_pin_cfg_t *wakeup_pin_cfg)
#if defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32WBAX) #if defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32WBAX)
/* Select the proper wake-up signal source */ /* Select the proper wake-up signal source */
if (wakeup_pin_cfg->src_selection & STM32_PWR_WKUP_PIN_SRC_0) { if (wakeup_pin_cfg->src_selection & STM32_PWR_WKUP_EVT_SRC_0) {
LL_PWR_SetWakeUpPinSignal0Selection(table_wakeup_pins[wkup_pin_index]); LL_PWR_SetWakeUpPinSignal0Selection(table_wakeup_pins[wkup_pin_index]);
} else if (wakeup_pin_cfg->src_selection & STM32_PWR_WKUP_PIN_SRC_1) { } else if (wakeup_pin_cfg->src_selection & STM32_PWR_WKUP_EVT_SRC_1) {
LL_PWR_SetWakeUpPinSignal1Selection(table_wakeup_pins[wkup_pin_index]); LL_PWR_SetWakeUpPinSignal1Selection(table_wakeup_pins[wkup_pin_index]);
} else if (wakeup_pin_cfg->src_selection & STM32_PWR_WKUP_PIN_SRC_2) { } else if (wakeup_pin_cfg->src_selection & STM32_PWR_WKUP_EVT_SRC_2) {
LL_PWR_SetWakeUpPinSignal2Selection(table_wakeup_pins[wkup_pin_index]); LL_PWR_SetWakeUpPinSignal2Selection(table_wakeup_pins[wkup_pin_index]);
} else { } else {
LL_PWR_SetWakeUpPinSignal3Selection(table_wakeup_pins[wkup_pin_index]); LL_PWR_SetWakeUpPinSignal3Selection(table_wakeup_pins[wkup_pin_index]);
@ -286,9 +286,9 @@ int stm32_pwr_wkup_pin_cfg_gpio(const struct gpio_dt_spec *gpio)
/* Each wake-up pin on STM32U5 is associated with 4 wkup srcs, 3 of them correspond to GPIOs. */ /* Each wake-up pin on STM32U5 is associated with 4 wkup srcs, 3 of them correspond to GPIOs. */
#if defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32WBAX) #if defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32WBAX)
wakeup_pin_cfg.src_selection = wkup_pin_gpio_cfg->dt_flags & wakeup_pin_cfg.src_selection = wkup_pin_gpio_cfg->dt_flags &
(STM32_PWR_WKUP_PIN_SRC_0 | (STM32_PWR_WKUP_EVT_SRC_0 |
STM32_PWR_WKUP_PIN_SRC_1 | STM32_PWR_WKUP_EVT_SRC_1 |
STM32_PWR_WKUP_PIN_SRC_2); STM32_PWR_WKUP_EVT_SRC_2);
#else #else
wakeup_pin_cfg.src_selection = 0; wakeup_pin_cfg.src_selection = 0;
#endif /* CONFIG_SOC_SERIES_STM32U5X or CONFIG_SOC_SERIES_STM32WBAX */ #endif /* CONFIG_SOC_SERIES_STM32U5X or CONFIG_SOC_SERIES_STM32WBAX */