diff --git a/dts/arm/renesas/rz/rzt/r9a07g074.dtsi b/dts/arm/renesas/rz/rzt/r9a07g074.dtsi new file mode 100644 index 00000000000..dc041ea8e51 --- /dev/null +++ b/dts/arm/renesas/rz/rzt/r9a07g074.dtsi @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + compatible = "renesas,r9a07g074"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-r52"; + reg = <0>; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + }; + + soc { + interrupt-parent = <&gic>; + + gic: interrupt-controller@94000000 { + compatible = "arm,gic-v3", "arm,gic"; + reg = <0x94000000 0x10000>, + <0x94100000 0x80000>; + interrupt-controller; + #interrupt-cells = <4>; + status = "okay"; + }; + + atcm: memory@0 { + compatible = "mmio-sram"; + reg = <0x00000000 DT_SIZE_K(512)>; + }; + + btcm: memory@100000 { + compatible = "mmio-sram"; + reg = <0x00100000 DT_SIZE_K(64)>; + }; + + sram: memory@10000000 { + compatible = "mmio-sram"; + reg = <0x10000000 DT_SIZE_M(1)>; + }; + + xspi1_cs0: memory@68000000 { + compatible = "mmio-sram"; + reg = <0x68000000 DT_SIZE_M(16)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader_param: partition@0 { + label = "loader-param"; + reg = <0x00000000 0x4C>; + read-only; + }; + + loader_program: partition@4C { + label = "loader-program"; + reg = <0x0000004C (DT_SIZE_K(56) - 0x4C)>; + read-only; + }; + + slot0_partition: partition@E000 { + label = "image-0"; + reg = <0x0000E000 (DT_SIZE_M(16) - DT_SIZE_K(56))>; + read-only; + }; + }; + }; + }; +}; diff --git a/soc/renesas/rz/rzt2l/CMakeLists.txt b/soc/renesas/rz/rzt2l/CMakeLists.txt new file mode 100644 index 00000000000..7633a8ff2a6 --- /dev/null +++ b/soc/renesas/rz/rzt2l/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + loader_param.c + ../common/loader_program.S +) + +zephyr_include_directories(.) + +zephyr_linker_sources(SECTIONS sections.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rz/rzt2l/Kconfig b/soc/renesas/rz/rzt2l/Kconfig new file mode 100644 index 00000000000..90fdc7792d5 --- /dev/null +++ b/soc/renesas/rz/rzt2l/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZT2L + select ARM + select CPU_CORTEX_R52 + select CPU_HAS_ARM_MPU + select GIC_SINGLE_SECURITY_STATE + select ARM_ARCH_TIMER + select HAS_RENESAS_RZ_FSP + select SOC_RESET_HOOK + select SOC_EARLY_INIT_HOOK + select ARM_CUSTOM_INTERRUPT_CONTROLLER diff --git a/soc/renesas/rz/rzt2l/Kconfig.defconfig b/soc/renesas/rz/rzt2l/Kconfig.defconfig new file mode 100644 index 00000000000..3a8c8b13c65 --- /dev/null +++ b/soc/renesas/rz/rzt2l/Kconfig.defconfig @@ -0,0 +1,30 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RZT2L + +config NUM_IRQS + default 480 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 + +config FPU + default y + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition + +config BUILD_OUTPUT_ADJUST_LMA + default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) + \ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)))" + +config BUILD_OUTPUT_ADJUST_LMA_SECTIONS + default "*;!.loader" + +endif # SOC_SERIES_RZT2L diff --git a/soc/renesas/rz/rzt2l/Kconfig.soc b/soc/renesas/rz/rzt2l/Kconfig.soc new file mode 100644 index 00000000000..6e2625b3200 --- /dev/null +++ b/soc/renesas/rz/rzt2l/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZT2L + bool + select SOC_FAMILY_RENESAS_RZ + help + Renesas RZ/T2L series + +config SOC_SERIES + default "rzt2l" if SOC_SERIES_RZT2L + +config SOC_R9A07G074M04GBG + bool + select SOC_SERIES_RZT2L + help + R9A07G074M04GBG + +config SOC + default "r9a07g074m04gbg" if SOC_R9A07G074M04GBG diff --git a/soc/renesas/rz/rzt2l/loader_param.c b/soc/renesas/rz/rzt2l/loader_param.c new file mode 100644 index 00000000000..7e948b3f72c --- /dev/null +++ b/soc/renesas/rz/rzt2l/loader_param.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#define CACHE_FLG (0x00000000) +#define CS0BCR_V_WRAPCFG_V (0x00000000) +#define CS0WCR_V_COMCFG_V (0x00000000) +#define DUMMY0_BMCFG_V (0x00000000) +#define BSC_FLG_xSPI_FLG (0x00000000) +#define LDR_ADDR_NML (0x6800004C) +#define LDR_SIZE_NML (0x00006000) +#define DEST_ADDR_NML (0x00102000) +#define DUMMY1 (0x00000000) +#define DUMMY2 (0x00000000) +#define DUMMY3_CSSCTL_V (0x0000003F) +#define DUMMY4_LIOCFGCS0_V (0x00070000) +#define DUMMY5 (0x00000000) +#define DUMMY6 (0x00000000) +#define DUMMY7 (0x00000000) +#define DUMMY8 (0x00000000) +#define DUMMY9 (0x00000000) +#define DUMMY10_ACCESS_SPEED (0x00000600) +#define CHECK_SUM (0xEEA2) +#define LOADER_PARAM_MAX (19) + +#define __loader_param Z_GENERIC_SECTION(.loader_param) + +const uint32_t loader_param[LOADER_PARAM_MAX] __loader_param = { + CACHE_FLG, + CS0BCR_V_WRAPCFG_V, + CS0WCR_V_COMCFG_V, + DUMMY0_BMCFG_V, + BSC_FLG_xSPI_FLG, + LDR_ADDR_NML, + LDR_SIZE_NML, + DEST_ADDR_NML, + DUMMY1, + DUMMY2, + DUMMY3_CSSCTL_V, + DUMMY4_LIOCFGCS0_V, + DUMMY5, + DUMMY6, + DUMMY7, + DUMMY8, + DUMMY9, + DUMMY10_ACCESS_SPEED, + CHECK_SUM, +}; diff --git a/soc/renesas/rz/rzt2l/pinctrl_soc.h b/soc/renesas/rz/rzt2l/pinctrl_soc.h new file mode 100644 index 00000000000..adcf52454b0 --- /dev/null +++ b/soc/renesas/rz/rzt2l/pinctrl_soc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZ_RZT2L_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZ_RZT2L_PINCTRL_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZ_RZT2L_PINCTRL_SOC_H_ */ diff --git a/soc/renesas/rz/rzt2l/sections.ld b/soc/renesas/rz/rzt2l/sections.ld new file mode 100644 index 00000000000..f1f3a9665b2 --- /dev/null +++ b/soc/renesas/rz/rzt2l/sections.ld @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +SECTION_PROLOGUE(.loader, CONFIG_FLASH_BASE_ADDRESS,) +{ + __loader_param_start = .; + KEEP(*(.loader_param)) + __loader_param_end = .; + . = DT_REG_ADDR(DT_NODELABEL(loader_program)); + __loader_program_start = .; + KEEP(*(.loader_text.*)) + __loader_program_end = .; +} GROUP_LINK_IN(FLASH) diff --git a/soc/renesas/rz/rzt2l/soc.c b/soc/renesas/rz/rzt2l/soc.c new file mode 100644 index 00000000000..28a554f6aa5 --- /dev/null +++ b/soc/renesas/rz/rzt2l/soc.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +extern void bsp_global_system_counter_init(void); + +void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES]; +IRQn_Type g_current_interrupt_num[32]; +uint8_t g_current_interrupt_pointer; + +void soc_reset_hook(void) +{ + /* Enable peripheral port access at EL1 and EL0 */ + __asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n"); + __asm__ volatile("orr r0, #1\n"); + __asm__ volatile("mcr p15, 0, r0, c15, c0, 0\n"); + barrier_dsync_fence_full(); + barrier_isync_fence_full(); +} + +void soc_early_init_hook(void) +{ + /* Configure system clocks. */ + bsp_clock_init(); + + /* Initialize SystemCoreClock variable. */ + SystemCoreClockUpdate(); + + /* Initialize global system counter. The counter is enabled and is incrementing. */ + bsp_global_system_counter_init(); +} + +unsigned int z_soc_irq_get_active(void) +{ + int intid = arm_gic_get_active(); + + g_current_interrupt_num[g_current_interrupt_pointer++] = intid; + + return intid; +} + +void z_soc_irq_eoi(unsigned int intid) +{ + g_current_interrupt_pointer--; + arm_gic_eoi(intid); +} + +void z_soc_irq_enable(unsigned int irq) +{ + arm_gic_irq_enable(irq); +} + +void z_soc_irq_disable(unsigned int irq) +{ + arm_gic_irq_disable(irq); +} + +int z_soc_irq_is_enabled(unsigned int irq) +{ + return arm_gic_irq_is_enabled(irq); +} + +void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) +{ + arm_gic_irq_set_priority(irq, prio, flags); +} + +void z_soc_irq_init(void) +{ + g_current_interrupt_pointer = 0; +} + +/* Porting FSP IRQ configuration by an empty function */ +/* Let Zephyr handle IRQ configuration */ +void bsp_irq_core_cfg(void) +{ + /* Do nothing */ +} diff --git a/soc/renesas/rz/rzt2l/soc.h b/soc/renesas/rz/rzt2l/soc.h new file mode 100644 index 00000000000..79436f6ad16 --- /dev/null +++ b/soc/renesas/rz/rzt2l/soc.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZT2L_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZT2L_SOC_H_ + +typedef enum IRQn { + SoftwareGeneratedInt0 = 0, + SoftwareGeneratedInt1, + SoftwareGeneratedInt2, + SoftwareGeneratedInt3, + SoftwareGeneratedInt4, + SoftwareGeneratedInt5, + SoftwareGeneratedInt6, + SoftwareGeneratedInt7, + SoftwareGeneratedInt8, + SoftwareGeneratedInt9, + SoftwareGeneratedInt10, + SoftwareGeneratedInt11, + SoftwareGeneratedInt12, + SoftwareGeneratedInt13, + SoftwareGeneratedInt14, + SoftwareGeneratedInt15, + DebugCommunicationsChannelInt = 22, + PerformanceMonitorCounterOverflowInt = 23, + CrossTriggerInterfaceInt = 24, + VritualCPUInterfaceMaintenanceInt = 25, + HypervisorTimerInt = 26, + VirtualTimerInt = 27, + NonSecurePhysicalTimerInt = 30, + SHARED_PERIPHERAL_INTERRUPTS_MAX_ENTRIES = CONFIG_NUM_IRQS +} IRQn_Type; + +/* Do not let CMSIS to handle GIC and Timer */ +#define __GIC_PRESENT 0 +#define __TIM_PRESENT 0 +#define __FPU_PRESENT 1 + +/* Porting FSP IRQ configuration by an empty function */ +/* Let Zephyr handle IRQ configuration */ +void bsp_irq_core_cfg(void); + +#endif /* ZEPHYR_SOC_RENESAS_RZT2L_SOC_H_ */ diff --git a/soc/renesas/rz/soc.yml b/soc/renesas/rz/soc.yml index 2a6fc79bede..df81bdff0ba 100644 --- a/soc/renesas/rz/soc.yml +++ b/soc/renesas/rz/soc.yml @@ -9,3 +9,6 @@ family: - name: rzn2l socs: - name: r9a07g084m04gbg + - name: rzt2l + socs: + - name: r9a07g074m04gbg