michaelh/zephyr
1
0
Fork 0
Code Releases Activity

arch: arm64: Parametrize registers usage for z_arm64_{enter,exit}_exc

Browse source 
Make explicit what registers we are going to be touched / modified when
using z_arm64_enter_exc and z_arm64_exit_exc.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione 2020-08-12 16:05:56 +02:00 • committed by Ioannis Glaropoulos
commit 310057d641
4 changed files with 23 additions and 23 deletions
Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/core/aarch64/isr_wrapper.S
View file

@ -33,7 +33,7 @@ GDATA(_sw_isr_table)
GTEXT(_isr_wrapper) GTEXT(_isr_wrapper)
SECTION_FUNC(TEXT, _isr_wrapper) SECTION_FUNC(TEXT, _isr_wrapper)
z_arm64_enter_exc z_arm64_enter_exc x0, x1, x2
/* ++(_kernel->nested) to be checked by arch_is_in_isr() */ /* ++(_kernel->nested) to be checked by arch_is_in_isr() */
ldr x0, =_kernel ldr x0, =_kernel
@ -108,5 +108,5 @@ exit:
#ifdef CONFIG_STACK_SENTINEL #ifdef CONFIG_STACK_SENTINEL
bl z_check_stack_sentinel bl z_check_stack_sentinel
#endif #endif
z_arm64_exit_exc z_arm64_exit_exc x0, x1, x2

36
arch/arm/core/aarch64/macro_priv.inc
View file

@ -19,7 +19,7 @@
* @return N/A * @return N/A
*/ */
.macro z_arm64_enter_exc .macro z_arm64_enter_exc xreg0, xreg1, xreg2
/* /*
* Two things can happen: * Two things can happen:
* *
@ -43,20 +43,20 @@
* Store SPSR_ELn and ELR_ELn. This is needed to support nested * Store SPSR_ELn and ELR_ELn. This is needed to support nested
* exception handlers * exception handlers
*/ */
switch_el x2, 3f, 2f, 1f switch_el \xreg0, 3f, 2f, 1f
3: 3:
mrs x0, spsr_el3 mrs \xreg1, spsr_el3
mrs x1, elr_el3 mrs \xreg2, elr_el3
b 0f b 0f
2: 2:
mrs x0, spsr_el2 mrs \xreg1, spsr_el2
mrs x1, elr_el2 mrs \xreg2, elr_el2
b 0f b 0f
1: 1:
mrs x0, spsr_el1 mrs \xreg1, spsr_el1
mrs x1, elr_el1 mrs \xreg2, elr_el1
0: 0:
stp x0, x1, [sp, #-16]! stp \xreg1, \xreg2, [sp, #-16]!
.endm .endm
/** /**
@ -71,24 +71,24 @@
* @return N/A * @return N/A
*/ */
.macro z_arm64_exit_exc .macro z_arm64_exit_exc xreg0, xreg1, xreg2
/* /*
* Restore SPSR_ELn and ELR_ELn. This is needed to support nested * Restore SPSR_ELn and ELR_ELn. This is needed to support nested
* exception handlers * exception handlers
*/ */
ldp x0, x1, [sp], #16 ldp \xreg0, \xreg1, [sp], #16
switch_el x2, 3f, 2f, 1f switch_el \xreg2, 3f, 2f, 1f
3: 3:
msr spsr_el3, x0 msr spsr_el3, \xreg0
msr elr_el3, x1 msr elr_el3, \xreg1
b 0f b 0f
2: 2:
msr spsr_el2, x0 msr spsr_el2, \xreg0
msr elr_el2, x1 msr elr_el2, \xreg1
b 0f b 0f
1: 1:
msr spsr_el1, x0 msr spsr_el1, \xreg0
msr elr_el1, x1 msr elr_el1, \xreg1
0: 0:
/* /*
* In x30 we can have: * In x30 we can have:

4
arch/arm/core/aarch64/swap_helper.S
View file

@ -152,7 +152,7 @@ SECTION_FUNC(TEXT, z_thread_entry_wrapper)
GTEXT(z_arm64_svc) GTEXT(z_arm64_svc)
SECTION_FUNC(TEXT, z_arm64_svc) SECTION_FUNC(TEXT, z_arm64_svc)
z_arm64_enter_exc z_arm64_enter_exc x0, x1, x2
switch_el x1, 3f, 2f, 1f switch_el x1, 3f, 2f, 1f
3: 3:
@ -208,7 +208,7 @@ context_switch:
bl z_arm64_context_switch bl z_arm64_context_switch
exit: exit:
z_arm64_exit_exc z_arm64_exit_exc x0, x1, x2
inv: inv:
mov x0, #0 /* K_ERR_CPU_EXCEPTION */ mov x0, #0 /* K_ERR_CPU_EXCEPTION */

2
arch/arm/core/aarch64/vector_table.S
View file

@ -90,7 +90,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
/* Current EL with SPx / SError */ /* Current EL with SPx / SError */
.align 7 .align 7
z_arm64_enter_exc z_arm64_enter_exc x0, x1, x2
mov x1, sp mov x1, sp
mov x0, #0 /* K_ERR_CPU_EXCEPTION */ mov x0, #0 /* K_ERR_CPU_EXCEPTION */