From 30fd0228ae3c5f7e51f098b6bdbfa8b04941b04b Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Fri, 18 Jun 2021 15:52:30 +0200 Subject: [PATCH] drivers: dma of the stm32 refactored macro for the dma-cells The macro to set the element of the dma-cells for each peripheral are defined in the dma_stm32 header file and used in the periph driver (as dma client) Signed-off-by: Francois Ramu --- drivers/serial/uart_stm32.c | 23 +++++++----------- drivers/spi/spi_ll_stm32.c | 26 ++++++++------------ include/drivers/dma/dma_stm32.h | 42 +++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+), 30 deletions(-) diff --git a/drivers/serial/uart_stm32.c b/drivers/serial/uart_stm32.c index 394b1474b87..5b74f60d95e 100644 --- a/drivers/serial/uart_stm32.c +++ b/drivers/serial/uart_stm32.c @@ -26,6 +26,7 @@ #ifdef CONFIG_UART_ASYNC_API #include +#include #include #endif @@ -1485,38 +1486,32 @@ static int uart_stm32_pm_control(const struct device *dev, #endif /* CONFIG_PM_DEVICE */ #ifdef CONFIG_UART_ASYNC_API -#define DMA_CHANNEL_CONFIG(id, dir) \ - DT_INST_DMAS_CELL_BY_NAME(id, dir, channel_config) -#define DMA_FEATURES(id, dir) \ - DT_INST_DMAS_CELL_BY_NAME(id, dir, features) -#define DMA_CTLR(id, dir) \ - DT_INST_DMAS_CTLR_BY_NAME(id, dir) /* src_dev and dest_dev should be 'MEMORY' or 'PERIPHERAL'. */ #define UART_DMA_CHANNEL_INIT(index, dir, dir_cap, src_dev, dest_dev) \ - .dma_dev = DEVICE_DT_GET(DMA_CTLR(index, dir)), \ + .dma_dev = DEVICE_DT_GET(STM32_DMA_CTLR(index, dir)), \ .dma_channel = DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \ .dma_cfg = { \ .dma_slot = DT_INST_DMAS_CELL_BY_NAME(index, dir, slot),\ .channel_direction = STM32_DMA_CONFIG_DIRECTION( \ - DMA_CHANNEL_CONFIG(index, dir)),\ + STM32_DMA_CHANNEL_CONFIG(index, dir)),\ .channel_priority = STM32_DMA_CONFIG_PRIORITY( \ - DMA_CHANNEL_CONFIG(index, dir)), \ + STM32_DMA_CHANNEL_CONFIG(index, dir)), \ .source_data_size = STM32_DMA_CONFIG_##src_dev##_DATA_SIZE(\ - DMA_CHANNEL_CONFIG(index, dir)),\ + STM32_DMA_CHANNEL_CONFIG(index, dir)),\ .dest_data_size = STM32_DMA_CONFIG_##dest_dev##_DATA_SIZE(\ - DMA_CHANNEL_CONFIG(index, dir)),\ + STM32_DMA_CHANNEL_CONFIG(index, dir)),\ .source_burst_length = 1, /* SINGLE transfer */ \ .dest_burst_length = 1, \ .block_count = 1, \ .dma_callback = uart_stm32_dma_##dir##_cb, \ }, \ .src_addr_increment = STM32_DMA_CONFIG_##src_dev##_ADDR_INC( \ - DMA_CHANNEL_CONFIG(index, dir)), \ + STM32_DMA_CHANNEL_CONFIG(index, dir)), \ .dst_addr_increment = STM32_DMA_CONFIG_##dest_dev##_ADDR_INC( \ - DMA_CHANNEL_CONFIG(index, dir)), \ + STM32_DMA_CHANNEL_CONFIG(index, dir)), \ .fifo_threshold = STM32_DMA_FEATURES_FIFO_THRESHOLD( \ - DMA_FEATURES(index, dir)), \ + STM32_DMA_FEATURES(index, dir)), \ #endif diff --git a/drivers/spi/spi_ll_stm32.c b/drivers/spi/spi_ll_stm32.c index 512bd1a87bd..529acc1d07d 100644 --- a/drivers/spi/spi_ll_stm32.c +++ b/drivers/spi/spi_ll_stm32.c @@ -19,6 +19,7 @@ LOG_MODULE_REGISTER(spi_ll_stm32); #include #ifdef CONFIG_SPI_STM32_DMA #include +#include #include #endif #include @@ -880,37 +881,30 @@ static void spi_stm32_irq_config_func_##id(const struct device *dev) \ #define STM32_SPI_IRQ_HANDLER(id) #endif -#define DMA_CHANNEL_CONFIG(id, dir) \ - DT_INST_DMAS_CELL_BY_NAME(id, dir, channel_config) -#define DMA_FEATURES(id, dir) \ - DT_INST_DMAS_CELL_BY_NAME(id, dir, features) -#define DMA_CTLR(id, dir) \ - DT_INST_DMAS_CTLR_BY_NAME(id, dir) - #define SPI_DMA_CHANNEL_INIT(index, dir, dir_cap, src_dev, dest_dev) \ - .dma_dev = DEVICE_DT_GET(DMA_CTLR(index, dir)), \ + .dma_dev = DEVICE_DT_GET(STM32_DMA_CTLR(index, dir)), \ .channel = DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \ .dma_cfg = { \ - .dma_slot = DT_INST_DMAS_CELL_BY_NAME(index, dir, slot),\ + .dma_slot = STM32_DMA_SLOT(index, dir, slot),\ .channel_direction = STM32_DMA_CONFIG_DIRECTION( \ - DMA_CHANNEL_CONFIG(index, dir)), \ + STM32_DMA_CHANNEL_CONFIG(index, dir)), \ .source_data_size = STM32_DMA_CONFIG_##src_dev##_DATA_SIZE( \ - DMA_CHANNEL_CONFIG(index, dir)), \ + STM32_DMA_CHANNEL_CONFIG(index, dir)), \ .dest_data_size = STM32_DMA_CONFIG_##dest_dev##_DATA_SIZE( \ - DMA_CHANNEL_CONFIG(index, dir)), \ + STM32_DMA_CHANNEL_CONFIG(index, dir)), \ .source_burst_length = 1, /* SINGLE transfer */ \ .dest_burst_length = 1, /* SINGLE transfer */ \ .channel_priority = STM32_DMA_CONFIG_PRIORITY( \ - DMA_CHANNEL_CONFIG(index, dir)),\ + STM32_DMA_CHANNEL_CONFIG(index, dir)),\ .dma_callback = dma_callback, \ .block_count = 2, \ }, \ .src_addr_increment = STM32_DMA_CONFIG_##src_dev##_ADDR_INC( \ - DMA_CHANNEL_CONFIG(index, dir)), \ + STM32_DMA_CHANNEL_CONFIG(index, dir)), \ .dst_addr_increment = STM32_DMA_CONFIG_##dest_dev##_ADDR_INC( \ - DMA_CHANNEL_CONFIG(index, dir)), \ + STM32_DMA_CHANNEL_CONFIG(index, dir)), \ .fifo_threshold = STM32_DMA_FEATURES_FIFO_THRESHOLD( \ - DMA_FEATURES(index, dir)), \ + STM32_DMA_FEATURES(index, dir)), \ #if CONFIG_SPI_STM32_DMA diff --git a/include/drivers/dma/dma_stm32.h b/include/drivers/dma/dma_stm32.h index 601f5d7fa79..b6ef4308bb2 100644 --- a/include/drivers/dma/dma_stm32.h +++ b/include/drivers/dma/dma_stm32.h @@ -12,4 +12,46 @@ */ #define STM32_DMA_HAL_OVERRIDE 0x7F +/* macro for dma slot (only for dma-v1 or dma-v2 types) */ +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v2bis) +#define STM32_DMA_SLOT(id, dir, slot) 0 +#else +#define STM32_DMA_SLOT(id, dir, slot) DT_INST_DMAS_CELL_BY_NAME(id, dir, slot) +#endif + +#define STM32_DMA_CHANNEL_CONFIG(id, dir) \ + DT_INST_DMAS_CELL_BY_NAME(id, dir, channel_config) +#define STM32_DMA_FEATURES(id, dir) \ + DT_INST_DMAS_CELL_BY_NAME(id, dir, features) +#define STM32_DMA_CTLR(id, dir) \ + DT_INST_DMAS_CTLR_BY_NAME(id, dir) + +/* macros for channel-config */ +/* direction defined on bits 6-7 */ +/* 0 -> MEM_TO_MEM, 1 -> MEM_TO_PERIPH, 2 -> PERIPH_TO_MEM */ +#define STM32_DMA_CONFIG_DIRECTION(config) ((config >> 6) & 0x3) +/* periph increment defined on bit 9 as true/false */ +#define STM32_DMA_CONFIG_PERIPHERAL_ADDR_INC(config) ((config >> 9) & 0x1) +/* mem increment defined on bit 10 as true/false */ +#define STM32_DMA_CONFIG_MEMORY_ADDR_INC(config) ((config >> 10) & 0x1) +/* perih data size defined on bits 11-12 */ +/* 0 -> 1 byte, 1 -> 2 bytes, 2 -> 4 bytes */ +#define STM32_DMA_CONFIG_PERIPHERAL_DATA_SIZE(config) \ + (1 << ((config >> 11) & 0x3)) +/* memory data size defined on bits 13, 14 */ +/* 0 -> 1 byte, 1 -> 2 bytes, 2 -> 4 bytes */ +#define STM32_DMA_CONFIG_MEMORY_DATA_SIZE(config) \ + (1 << ((config >> 13) & 0x3)) +/* priority increment offset defined on bit 15 */ +#define STM32_DMA_CONFIG_PERIPHERAL_INC_FIXED(config) ((config >> 15) & 0x1) +/* priority defined on bits 16-17 as 0, 1, 2, 3 */ +#define STM32_DMA_CONFIG_PRIORITY(config) ((config >> 16) & 0x3) + +/* macro for features (only for dma-v1) */ +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v1) +#define STM32_DMA_FEATURES_FIFO_THRESHOLD(features) (features & 0x3) +#else +#define STM32_DMA_FEATURES_FIFO_THRESHOLD(features) 0 +#endif + #endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_STM32_H_ */