boards: arm: stm32h735g_disco: Enable ADC support
Enable ADC support for the stm32h735g_disco board in devicetree Signed-off-by: Ben Marsh <ben.marsh@helvar.com>
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6d55cc6c23
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30e0fa82f8
6 changed files with 43 additions and 2 deletions
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@ -63,6 +63,8 @@ The current Zephyr stm32h735g_disco board configuration supports the following h
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+-----------+------------+-------------------------------------+
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+-----------+------------+-------------------------------------+
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| FMC | on-chip | memc (SDRAM) |
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| FMC | on-chip | memc (SDRAM) |
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+-----------+------------+-------------------------------------+
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+-----------+------------+-------------------------------------+
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| ADC | on-chip | ADC Controller |
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+-----------+------------+-------------------------------------+
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Other hardware features are not yet supported on Zephyr porting.
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Other hardware features are not yet supported on Zephyr porting.
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@ -106,6 +106,12 @@
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status = "okay";
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status = "okay";
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};
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};
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&adc1 {
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pinctrl-0 = <&adc1_inp0_pa0_c>;
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pinctrl-names = "default";
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status = "okay";
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};
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&mac {
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&mac {
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pinctrl-0 = <ð_mdc_pc1
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pinctrl-0 = <ð_mdc_pc1
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ð_rxd0_pc4
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ð_rxd0_pc4
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@ -13,3 +13,4 @@ supported:
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- gpio
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- gpio
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- netif:eth
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- netif:eth
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- memc
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- memc
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- adc
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24
samples/drivers/adc/boards/stm32h735g_disco.overlay
Normal file
24
samples/drivers/adc/boards/stm32h735g_disco.overlay
Normal file
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@ -0,0 +1,24 @@
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/* Copyright (c) 2021 STMicroelectronics
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SPDX-License-Identifier: Apache-2.0 */
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#include <zephyr/dt-bindings/adc/adc.h>
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/ {
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zephyr,user {
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/* adjust channel number according to pinmux in board.dts */
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io-channels = <&adc1 0>;
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};
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};
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&adc1 {
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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zephyr,gain = "ADC_GAIN_1";
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zephyr,reference = "ADC_REF_INTERNAL";
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zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
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zephyr,resolution = <16>;
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};
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};
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@ -4,8 +4,8 @@ tests:
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sample.drivers.adc:
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sample.drivers.adc:
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tags: ADC
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tags: ADC
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depends_on: adc
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depends_on: adc
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platform_allow: nucleo_l073rz disco_l475_iot1 cc3220sf_launchxl
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platform_allow: nucleo_l073rz disco_l475_iot1 cc3220sf_launchxl cc3235sf_launchxl
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cc3235sf_launchxl stm32l496g_disco nrf51dk_nrf51422 nrf52840dk_nrf52840
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stm32l496g_disco stm32h735g_disco nrf51dk_nrf51422 nrf52840dk_nrf52840
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mec172xevb_assy6906 gd32f350r_eval gd32f450i_eval gd32vf103v_eval gd32f403z_eval
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mec172xevb_assy6906 gd32f350r_eval gd32f450i_eval gd32vf103v_eval gd32f403z_eval
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esp32 esp32s2_saola esp32c3_devkitm gd32l233r_eval
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esp32 esp32s2_saola esp32c3_devkitm gd32l233r_eval
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integration_platforms:
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integration_platforms:
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@ -239,6 +239,14 @@
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/* Some F3 series SOCs do not have channel 0 connected to an external GPIO. */
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/* Some F3 series SOCs do not have channel 0 connected to an external GPIO. */
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#define ADC_1ST_CHANNEL_ID 1
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#define ADC_1ST_CHANNEL_ID 1
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#elif defined(CONFIG_BOARD_STM32H735G_DISCO)
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#define ADC_DEVICE_NODE DT_INST(0, st_stm32_adc)
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#define ADC_RESOLUTION 16
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#define ADC_GAIN ADC_GAIN_1
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#define ADC_REFERENCE ADC_REF_INTERNAL
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#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT
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#define ADC_1ST_CHANNEL_ID 0
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#elif defined(CONFIG_BOARD_NUCLEO_L476RG) || \
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#elif defined(CONFIG_BOARD_NUCLEO_L476RG) || \
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defined(CONFIG_BOARD_BLACKPILL_F411CE) || \
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defined(CONFIG_BOARD_BLACKPILL_F411CE) || \
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defined(CONFIG_BOARD_STM32F401_MINI) || \
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defined(CONFIG_BOARD_STM32F401_MINI) || \
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