From 30b3a5ffe73eec136258dcf6c8ab80ec8fce1b9c Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 4 Mar 2022 11:07:47 +0100 Subject: [PATCH] drivers/clock_control: stm32u5: Centralize regu voltage setting Similar to other general settings, centralize regu voltage setting. Signed-off-by: Erwan Gouriou --- drivers/clock_control/clock_stm32_ll_u5.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_u5.c b/drivers/clock_control/clock_stm32_ll_u5.c index 2f5e58f51eb..b477ac949ea 100644 --- a/drivers/clock_control/clock_stm32_ll_u5.c +++ b/drivers/clock_control/clock_stm32_ll_u5.c @@ -314,8 +314,6 @@ void config_src_sysclk_pll(LL_UTILS_ClkInitTypeDef s_ClkInitStruct) LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR); } - set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); - if (IS_ENABLED(STM32_PLL_SRC_MSIS)) { set_up_clk_msis(); @@ -382,8 +380,6 @@ void config_src_sysclk_msis(LL_UTILS_ClkInitTypeDef s_ClkInitStruct) { #ifdef STM32_SYSCLK_SRC_MSIS - set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); - /* Set MSIS as SYSCLCK source */ set_up_clk_msis(); LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSIS); @@ -415,6 +411,9 @@ int stm32_clock_control_init(const struct device *dev) /* configure clock for AHB/APB buses */ config_bus_clk_init((LL_UTILS_ClkInitTypeDef *)&s_ClkInitStruct); + /* Set voltage regulator to comply with targeted system frequency */ + set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); + /* Current hclk value */ old_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(get_startup_frequency(), LL_RCC_GetAHBPrescaler());