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tests: drivers: stm32 clock control testing on stm32wl55

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target is stm32wl55 with clearing clock config
target is stm32wl55 with pll 48MHz from hsi clock config
target is stm32wl55 with pll 48MHz from hse clock config
target is stm32wl55 with hse clock config (no pll)
target is stm32wl55 with msi clock config (no pll)

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2022-03-01 11:59:18 +01:00 • committed by Maureen Helm
commit 30a65dc6d1
6 changed files with 167 additions and 1 deletions
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20
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/msi_range11.overlay Normal file
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@ -0,0 +1,20 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that applies after clear all clocks with .overlay file.
*/
&clk_msi {
status = "okay";
msi-range = <11>;
};
&rcc {
clocks = <&clk_msi>;
clock-frequency = <DT_FREQ_M(48)>;
};

29
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_48_hsi_16.overlay Normal file
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@ -0,0 +1,29 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <6>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
};

22
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/wl_32_hse.overlay Normal file
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@ -0,0 +1,22 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
* It applies to the stm32wl where the hse prescaler is 1 and by-passed
*/
&clk_hse {
hse-tcxo;
clock-frequency = <DT_FREQ_M(32)>; /* STLink 32MHz clock */
status = "okay";
};
&rcc {
clocks = <&clk_hse>;
clock-frequency = <DT_FREQ_M(32)>;
};

50
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/wl_clear_clocks.overlay Normal file
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@ -0,0 +1,50 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay clears clocks back to a state equivalent to what could
* be found in stm32wl.dtsi
*/
&clk_hse {
status = "disabled";
/delete-property/ hse-tcxo;
/delete-property/ hse-div2;
/delete-property/ clock-frequency;
};
&clk_hsi {
status = "disabled";
/delete-property/ hsi-div;
};
&clk_lse {
status = "disabled";
};
&clk_lsi {
status = "disabled";
};
&clk_msi {
status = "disabled";
/delete-property/ msi-range;
};
&pll {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-p;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&rcc {
/delete-property/ clocks;
/delete-property/ clock-frequency;
};

33
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/wl_pll_48_hse_32.overlay Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
* It applies to the stm32wl where the hse prescaler is 2 and by-passed
*/
&clk_hse {
hse-tcxo;
hse-div2;
clock-frequency = <DT_FREQ_M(32)>; /* STLink 32MHz clock */
status = "okay";
};
&pll {
div-m = <2>;
mul-n = <12>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
};

14
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml
View file

@ -9,7 +9,7 @@ tests:
platform_allow: nucleo_g071rb nucleo_g474re
drivers.stm32_clock_configuration.common.sysclksrc_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_g071rb nucleo_l152re nucleo_l073rz
platform_allow: nucleo_g071rb nucleo_l152re nucleo_l073rz nucleo_wl55jc
drivers.stm32_clock_configuration.common.sysclksrc_hse_24:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_24.overlay"
platform_allow: nucleo_g474re
@ -28,3 +28,15 @@ tests:
drivers.stm32_clock_configuration.common.sysclksrc_msi_range6:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/msi_range6.overlay"
platform_allow: nucleo_l152re nucleo_l073rz
drivers.stm32_clock_configuration.common.sysclksrc_pll_48_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/pll_48_hsi_16.overlay"
platform_allow: nucleo_wl55jc
drivers.stm32_clock_configuration.common.sysclksrc_pll_48_hse_32:
extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/wl_pll_48_hse_32.overlay"
platform_allow: nucleo_wl55jc
drivers.stm32_clock_configuration.common.sysclksrc_32_hse:
extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/wl_32_hse.overlay"
platform_allow: nucleo_wl55jc
drivers.stm32_clock_configuration.common.sysclksrc_48_msi:
extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/msi_range11.overlay"
platform_allow: nucleo_wl55jc