boards: mps3: Add support for corstone300/an552

What is changed?
 - Added a new mps3 board an552 for the soc corstone300.
   The qualifier to build/run application with board mps3/an552 is
   `mps3/corstone300/an552` for secure and
   `mps3/corstone300/an552/ns` for non-secure.
 - Added FVP variant to enable FVP testing with corstone300
   and it uses the ARM FVP `FVP_Corstone_SSE-300_Ethos-U55`.
   The qualifier to build/run application with FVP is
   `mps3/corstone300/fvp` for secure and
   `mps3/corstone300/fvp/ns` for non-secure.
 - Note: the qualifier to build/run application with board mps3/an547
   is now changed to
   `mps3/corstone300/an547` for secure and
   `mps3/corstone300/an547/ns` for non-secure.

How is it changed?
 - Moved common code from mps3/an547 to corstone300.
 - Renamed soc for an547 to corstone300 and added
   a new soc corstone300/an552.

Why do we need this change?
 - This enables FVP support and testing for corstone300.
 - SOC/qualifier for mps3/an547 was renamed to reduce code redundancy
 - A separate FVP variant was added for AN552 because, the TFM board
   used for non-secure variant differs for FPGA and FVP.
   TFM board `arm/mps3/corstone300/fvp` should be used when testing
   AN552 with FVP and `arm/mps3/corstone300/an552` should be used when
   testing with AN552 FPGA.

Signed-off-by: Sudan Landge <sudan.landge@arm.com>

boards/arm/mps3/Kconfig

@@ -1,5 +1,6 @@
 # Copyright (c) 2021 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_MPS3
-	select QEMU_TARGET
+	select QEMU_TARGET if BOARD_MPS3_CORSTONE300_AN547 || BOARD_MPS3_CORSTONE300_AN547_NS

boards/arm/mps3/Kconfig.defconfig

@@ -1,7 +1,8 @@
 # Copyright (c) 2018-2021 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
-if BOARD_MPS3_AN547
+if BOARD_MPS3_CORSTONE300_AN547 || BOARD_MPS3_CORSTONE300_AN552 || BOARD_MPS3_CORSTONE300_FVP
 
 # MPU-based null-pointer dereferencing detection cannot
 # be applied as the (0x0 - 0x400) is unmapped but QEMU

boards/arm/mps3/Kconfig.mps3

@@ -1,7 +1,13 @@
 # Copyright (c) 2023 Nordic Semiconductor
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 #
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_MPS3
 	select SOC_SERIES_MPS3
-	select SOC_MPS3_AN547
+	select SOC_MPS3_CORSTONE300 if  BOARD_MPS3_CORSTONE300_AN547    || \
+					BOARD_MPS3_CORSTONE300_AN547_NS || \
+					BOARD_MPS3_CORSTONE300_AN552    || \
+					BOARD_MPS3_CORSTONE300_AN552_NS || \
+					BOARD_MPS3_CORSTONE300_FVP      || \
+					BOARD_MPS3_CORSTONE300_FVP_NS

boards/arm/mps3/board.cmake

@@ -1,24 +1,36 @@
 # Copyright (c) 2021 Linaro
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
-# The AN547 FVP must be used to enable Ethos-U55 NPU support, but QEMU also
+# The FVP variant must be used to enable Ethos-U55 NPU support, but QEMU also
 # supports the AN547 without the NPU.
 #
-# For emulation, QEMU is used by default. To use AN547 FVP as an emulation
+# Default emulation:
-# use the 'run_armfvp' target, for example:
+#     QEMU is used by default for corstone300/an547 and
+#     FVP  is used by default for corstone300/fvp.
 #
-# $ west build -b mps3_an547 samples/hello_world -t run_armfvp
 
-set(SUPPORTED_EMU_PLATFORMS qemu armfvp)
 
-# QEMU settings
+if(CONFIG_BOARD_MPS3_CORSTONE300_AN547 OR CONFIG_BOARD_MPS3_CORSTONE300_AN547_NS)
-set(QEMU_CPU_TYPE_${ARCH} cortex-m55)
+  set(SUPPORTED_EMU_PLATFORMS qemu)
-set(QEMU_FLAGS_${ARCH}
+
-  -cpu ${QEMU_CPU_TYPE_${ARCH}}
+  # QEMU settings
-  -machine mps3-an547
+  set(QEMU_CPU_TYPE_${ARCH} cortex-m55)
-  -nographic
+  set(QEMU_FLAGS_${ARCH}
-  -vga none
+    -cpu ${QEMU_CPU_TYPE_${ARCH}}
-  )
+    -machine mps3-an547
+    -nographic
+    -vga none
+    )
+elseif(CONFIG_BOARD_MPS3_CORSTONE300_FVP OR CONFIG_BOARD_MPS3_CORSTONE300_FVP_NS)
+  set(SUPPORTED_EMU_PLATFORMS armfvp)
+  set(ARMFVP_BIN_NAME FVP_Corstone_SSE-300_Ethos-U55)
+elseif(CONFIG_BOARD_MPS3_CORSTONE300)
+  string(REPLACE "mps3/corstone300;" "" board_targets "${board_targets}")
+  string(REPLACE ";" "\n" board_targets "${board_targets}")
+  message(FATAL_ERROR "Please use a target from the list below: \n${board_targets}\n")
+endif()
+
 board_set_debugger_ifnset(qemu)
 
 if (CONFIG_BUILD_WITH_TFM)
@@ -28,14 +40,11 @@ if (CONFIG_BUILD_WITH_TFM)
   set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex")
 endif()
 
-# FVP settings
-set(ARMFVP_BIN_NAME FVP_Corstone_SSE-300_Ethos-U55)
-
 # FVP Parameters
 # -C indicate a config option in the form of:
 #   instance.parameter=value
 # Run the FVP with --list-params to list all options
-set(ARMFVP_FLAGS
+set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
   -C mps3_board.uart0.out_file=-
   -C mps3_board.uart0.unbuffered_output=1
   -C mps3_board.uart1.out_file=-
@@ -43,4 +52,7 @@ set(ARMFVP_FLAGS
   -C mps3_board.uart2.out_file=-
   -C mps3_board.uart2.unbuffered_output=1
   -C mps3_board.visualisation.disable-visualisation=1
+  -C mps3_board.telnetterminal0.start_telnet=0
+  -C mps3_board.telnetterminal1.start_telnet=0
+  -C mps3_board.telnetterminal2.start_telnet=0
   )

boards/arm/mps3/board.yml

@@ -3,6 +3,14 @@ board:
   full_name: MPS3 AN547
   vendor: arm
   socs:
-  - name: 'an547'
+  - name: 'corstone300'
     variants:
-    - name: 'ns'
+    - name: 'an547'
+      variants:
+      - name: 'ns'
+    - name: 'an552'
+      variants:
+      - name: 'ns'
+    - name: 'fvp'
+      variants:
+      - name: 'ns'

boards/arm/mps3/doc/index.rst

@@ -1,61 +1,133 @@
-.. _mps3_an547_board:
+.. _mps3_board:
 
-ARM MPS3 AN547
+ARM MPS3
 ###############
 
 Overview
 ********
 
-The mps3_an547 board configuration is used by Zephyr applications that run
+The mps3 board configuration is used by Zephyr applications that run
-on the MPS3 AN547 board. It provides support for the MPS3 AN547 ARM Cortex-M55
+on the MPS3 board. It provides support for the following devices:
-CPU and the following devices:
 
 - Nested Vectored Interrupt Controller (NVIC)
 - System Tick System Clock (SYSTICK)
 - Cortex-M System Design Kit GPIO
 - Cortex-M System Design Kit UART
 - Ethos-U55 NPU
+- AN547 and AN552 support Arm Cortex-M55 CPU
 
-.. image:: img/mps3_an547.jpg
+.. image:: img/mps3.jpg
      :align: center
-     :alt: ARM MPS3 AN547
+     :alt: ARM MPS3
 
-This board configuration also supports using the `Corstone-300 FVP`_ to emulate
+`Corstone-300 FVP`_ (Fixed Virtual Platforms) is a complete
-a MPS3 AN547 hardware platform.
+simulations of the Arm system, including processor, memory and peripherals.
+They are available free of charge for Linux and Windows systems.
+The FVPs have been selected for simulation since they provide access to the
+Ethos-U55 NPU, which is unavailable in QEMU or other simulation platforms.
 
-The Corstone-300 FVP (Fixed Virtual Platform) is a complete simulation of the
-Arm system, including processor, memory and peripherals. It is a available free
-of charge for Linux and Windows systems. The FVP has been selected for
-simulation since it provides access to the Ethos-U55 NPU, which is unavailable
-in QEMU or other simulation platforms.
-
-To run the Fixed Virtual Platform simulation tool you must download "FVP model
-for the Corstone-300 MPS3" from Arm and install it on your host PC. This board
-has been tested with version 11.12.57 (Nov  2 2020).
 
 Zephyr board options
 ====================
 
-The MPS3+ AN547 is an SoC with Cortex-M55 architecture. Zephyr provides support
+.. tabs::
-for building for both Secure and Non-Secure firmware.
 
-The BOARD options are summarized below:
+  .. tab:: MPS3 Corstone-300 (AN547)
 
-+----------------------+-----------------------------------------------+
+   The MPS3+ AN547 is an SoC with Cortex-M55 architecture. Zephyr provides support
-|   BOARD              | Description                                   |
+   for building for both Secure and Non-Secure firmware.
-+======================+===============================================+
+
-| ``mps3/an547``       | For building Secure (or Secure-only) firmware |
+   The BOARD options are summarized below:
-+----------------------+-----------------------------------------------+
+
-| ``mps3/an547/ns``    | For building Non-Secure firmware              |
+   +-------------------------------+-----------------------------------------------+
-+----------------------+-----------------------------------------------+
+   |   BOARD                       | Description                                   |
+   +===============================+===============================================+
+   | ``mps3/corstone300/an547``    | For building Secure (or Secure-only) firmware |
+   +-------------------------------+-----------------------------------------------+
+   | ``mps3/corstone300/an547/ns`` | For building Non-Secure firmware              |
+   +-------------------------------+-----------------------------------------------+
+
+   FPGA Usage:
+    - Follow `Programming and Debugging`_ for build and flash instructions.
+
+   FVP Usage:
+    - FVP is not supported for this variant.
+
+   QEMU Usage:
+    - To run with QEMU instead of the default FVP, override the emulator selection at build time via:
+
+    .. code-block:: bash
+
+     $ west build -b mps3_an547 samples/hello_world -DEMU_PLATFORM=qemu -t run
+
+  .. tab:: MPS3 Corstone-300 (AN552)
+
+   The MPS3+ AN552 is an SoC with Cortex-M55 architecture. Zephyr provides support
+   for building for both Secure and Non-Secure firmware.
+
+   The BOARD options are summarized below:
+
+   +-------------------------------+-----------------------------------------------+
+   |   BOARD                       | Description                                   |
+   +===============================+===============================================+
+   | ``mps3/corstone300/an552``    | For building Secure (or Secure-only) firmware |
+   +-------------------------------+-----------------------------------------------+
+   | ``mps3/corstone300/an552/ns`` | For building Non-Secure firmware              |
+   +-------------------------------+-----------------------------------------------+
+
+   FPGA Usage:
+    - Follow `Programming and Debugging`_ for build and flash instructions.
+
+   FVP Usage:
+    - FVP not supported for this variant.
+
+   QEMU Usage:
+    - QEMU not supported for this variant of board.
+
+  .. tab:: MPS3 Corstone-300 (FVP)
+
+   The MPS3+ FVP is an SoC with Cortex-M55 architecture. Zephyr provides support
+   for building for both Secure and Non-Secure firmware.
+
+   The BOARD options are summarized below:
+
+   +-------------------------------+-----------------------------------------------+
+   |   BOARD                       | Description                                   |
+   +===============================+===============================================+
+   | ``mps3/corstone300/fvp``      | For building Secure (or Secure-only) firmware |
+   +-------------------------------+-----------------------------------------------+
+   | ``mps3/corstone300/fvp/ns``   | For building Non-Secure firmware              |
+   +-------------------------------+-----------------------------------------------+
+
+   FVP Usage:
+    - To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before using it. Then you can run it with ``west build -t run``.
+
+    .. code-block:: bash
+
+       export ARMFVP_BIN_PATH=/path/to/fvp/directory
+       west build -b {BOARD qualifier from table above} samples/hello_world -t run
+
+   To run the Fixed Virtual Platform simulation tool you must download "FVP model
+   for the Corstone-300 MPS3" from Arm and install it on your host PC. This board
+   has been tested with version 11.24.13 (Jan  4 2024).
+
+   QEMU Usage:
+    - QEMU not supported for this variant of board.
+
+  .. note::
+     Board qualifier must include the board name as mentioned above.
+     ``mps3/corstone300`` without the board name is not a valid qualifier.
 
 Hardware
 ********
 
-ARM MPS3 AN547 provides the following hardware components:
+ARM MPS3 provides the following hardware components:
+
+- CPU
+
+  - AN547 and AN552 support Arm Cortex-M55 CPU and
+    Soft Macro Model (SMM) implementation of SSE-300 subsystem
 
-- ARM Cortex-M55
-- Soft Macro Model (SMM) implementation of SSE-300 subsystem
 - Memory
 
   - 8MB BRAM
@@ -89,7 +161,7 @@ ARM MPS3 AN547 provides the following hardware components:
 Supported Features
 ===================
 
-The ``mps3/an547`` board configuration supports the following hardware features:
+The ``MPS3`` board configuration supports the following hardware features:
 
 +-----------+------------+-------------------------------------+
 | Interface | Controller | Driver/Component                    |
@@ -109,14 +181,15 @@ See the `MPS3 FPGA Website`_ for a complete list of MPS3 AN547 board hardware
 features.
 
 The default configuration can be found in
-:zephyr_file:`boards/arm/mps3/mps3_an547_defconfig`.
+ - For AN547: :zephyr_file:`boards/arm/mps3/mps3_corstone300_an547_defconfig`.
+ - For AN552: :zephyr_file:`boards/arm/mps3/mps3_corstone300_an552_defconfig`.
+ - For FVP  : :zephyr_file:`boards/arm/mps3/mps3_corstone300_fvp_defconfig`.
 
-For more details refer to `MPS3 AN547 Technical Reference Manual (TRM)`_.
 
 Serial Port
 ===========
 
-The MPS3 AN547 has six UARTs. The Zephyr console output by default, uses
+The MPS3 has six UARTs. The Zephyr console output by default, uses
 UART0, which is exposed over the Debug USB interface (J8).
 
 Serial port 0 on the Debug USB interface is the MCC board control console.
@@ -127,26 +200,28 @@ Serial port 2 on the Debug USB interface is connected to UART 1.
 
 Serial port 3 on the Debug USB interface is connected to UART 2.
 
+.. Programming and Debugging:
+
 Programming and Debugging
 *************************
 
 Flashing
 ========
 
-MPS3 AN547 provides:
+MPS3 provides:
 
 - A USB connection to the host computer, which exposes Mass Storage and
   CMSIS-DAP, and serial ports.
 
-Building an application
+Building an application with AN547
------------------------
+----------------------------------
 
 You can build applications in the usual way. Here is an example for
-the :zephyr:code-sample:`hello_world` application.
+the :zephyr:code-sample:`hello_world` application with AN547.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: mps3/an547
+   :board: mps3/corstone300/an547
    :goals: build
 
 Open a serial terminal (minicom, putty, etc.) with the following settings:
@@ -178,7 +253,7 @@ The update requires 3 steps:
 
 1. Copy application files to ``<MPS3 device name>/SOFTWARE/``.
 2. Open ``<MPS3 device name>/MB/HBI0309C/AN547/images.txt``.
-3. Update the ``AN547/images.txt`` file as follows:
+3. Update the ``images.txt`` file as follows:
 
 .. code-block:: bash
 
@@ -200,31 +275,12 @@ serial port:
    Hello World! mps3
 
 
-FVP Usage
+For more details refer to:
-=========
+ - `MPS3 AN547 Technical Reference Manual (TRM)`_
-
+ - `MPS3 AN552 Technical Reference Manual (TRM)`_
-To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before
+ - `MPS3 FPGA Prototyping Board Technical Reference Manual (TRM)`_
-using it. Then you can run it with ``west build -t run``.
+ - `Cortex M55 Generic User Guide`_
-
+ - `Corelink SSE-300 Example Subsystem`_
-.. code-block:: bash
-
-   export ARMFVP_BIN_PATH=/path/to/fvp/directory
-   west build -t run
-
-
-QEMU Usage
-==========
-
-To run with QEMU instead of the default FVP, override the emulator selection
-at build time via:
-
-.. code-block:: bash
-
-   $ west build -b mps3_an547 samples/hello_world -DEMU_PLATFORM=qemu -t run
-
-
-Note, however, that the Ethos-U55 NPU is not available in QEMU. If you require
-the use of the NPU, please use the default FVP for device emulation.
 
 .. _Corstone-300 FVP:
    https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
@@ -235,6 +291,9 @@ the use of the NPU, please use the default FVP for device emulation.
 .. _MPS3 AN547 Technical Reference Manual (TRM):
    https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf
 
+.. _MPS3 AN552 Technical Reference Manual (TRM):
+   https://developer.arm.com/documentation/dai0552/latest
+
 .. _MPS3 FPGA Prototyping Board Technical Reference Manual (TRM):
    https://developer.arm.com/documentation/100765/latest
 

boards/arm/mps3/mps3_common.dtsi

@@ -0,0 +1,98 @@
+/*
+ * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* /dts-v1/; */
+
+#include <arm/armv8.1-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <mem.h>
+
+/ {
+	aliases {
+		led0 = &led_0;
+		led1 = &led_1;
+		sw0 = &user_button_0;
+		sw1 = &user_button_1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led_0: led_0 {
+			gpios = <&gpio_led0 0>;
+			label = "USERLED0";
+		};
+		led_1: led_1 {
+			gpios = <&gpio_led0 1>;
+			label = "USERLED1";
+		};
+		led_2: led_2 {
+			gpios = <&gpio_led0 2>;
+			label = "USERLED2";
+		};
+		led_3: led_3 {
+			gpios = <&gpio_led0 3>;
+			label = "USERLED3";
+		};
+		led_4: led_4 {
+			gpios = <&gpio_led0 4>;
+			label = "USERLED4";
+		};
+		led_5: led_5 {
+			gpios = <&gpio_led0 5>;
+			label = "USERLED5";
+		};
+		led_6: led_6 {
+			gpios = <&gpio_led0 6>;
+			label = "USERLED6";
+		};
+		led_7: led_7 {
+			gpios = <&gpio_led0 7>;
+			label = "USERLED7";
+		};
+		led_8: led_8 {
+			gpios = <&gpio_led0 8>;
+			label = "PB1LED";
+		};
+		led_9: led_9 {
+			gpios = <&gpio_led0 9>;
+			label = "PB2LED";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button_0: button_0 {
+			label = "USERPB0";
+			gpios = <&gpio_button 0>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+		user_button_1: button_1 {
+			label = "USERPB1";
+			gpios = <&gpio_button 1>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	/* DDR4 - 2G, alternates non-secure/secure every 256M */
+	ddr4: memory@60000000 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_M(256)
+		       0x70000000 DT_SIZE_M(256)
+		       0x80000000 DT_SIZE_M(256)
+		       0x90000000 DT_SIZE_M(256)
+		       0xa0000000 DT_SIZE_M(256)
+		       0xb0000000 DT_SIZE_M(256)
+		       0xc0000000 DT_SIZE_M(256)
+		       0xd0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};

boards/arm/mps3/mps3_common_soc_peripheral.dtsi

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019-2021 Linaro Limited
+ * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -66,20 +67,50 @@ i2c_audio_conf: i2c@9201000 {
 	reg = <0x9201000 0x1000>;
 };
 
-i2c_shield0: i2c@9203000 {
+spi_adc: spi@9202000 {
-	compatible = "arm,versatile-i2c";
+	compatible = "arm,pl022";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
+	reg = <0x9202000 DT_SIZE_K(4)>;
+	interrupts = <53 3>;
+	interrupt-names = "shield_adc";
+	clocks = <&sysclk>;
 	#address-cells = <1>;
 	#size-cells = <0>;
-	reg = <0x9203000 0x1000>;
 };
 
-i2c_shield1: i2c@9204000 {
+spi_shield0: spi@9203000 {
+	compatible = "arm,pl022";
+	reg = <0x9203000 DT_SIZE_K(4)>;
+	interrupts = <54 3>;
+	interrupt-names = "shield0_spi";
+	clocks = <&sysclk>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+};
+
+spi_shield1: spi@9204000 {
+	compatible = "arm,pl022";
+	reg = <0x9204000 DT_SIZE_K(4)>;
+	interrupts = <55 3>;
+	interrupt-names = "shield1_spi";
+	clocks = <&sysclk>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+};
+
+i2c_shield0: i2c@9205000 {
 	compatible = "arm,versatile-i2c";
 	clock-frequency = <I2C_BITRATE_STANDARD>;
 	#address-cells = <1>;
 	#size-cells = <0>;
-	reg = <0x9204000 0x1000>;
+	reg = <0x9205000 0x1000>;
+};
+
+i2c_shield1: i2c@9206000 {
+	compatible = "arm,versatile-i2c";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0x9206000 0x1000>;
 };
 
 i2c_ddr4_eeprom: i2c@9208000 {

boards/arm/mps3/mps3_corstone300_an547.dts

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018-2021 Linaro Limited
- * Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,19 +11,13 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
+#include "mps3_common.dtsi"
 
 / {
 	compatible = "arm,mps3-an547";
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	aliases {
-		led0 = &led_0;
-		led1 = &led_1;
-		sw0 = &user_button_0;
-		sw1 = &user_button_1;
-	};
-
 	chosen {
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
@@ -31,79 +25,6 @@
 		zephyr,flash = &itcm;
 	};
 
-	leds {
-		compatible = "gpio-leds";
-		led_0: led_0 {
-			gpios = <&gpio_led0 0>;
-			label = "USERLED0";
-		};
-		led_1: led_1 {
-			gpios = <&gpio_led0 1>;
-			label = "USERLED1";
-		};
-		led_2: led_2 {
-			gpios = <&gpio_led0 2>;
-			label = "USERLED2";
-		};
-		led_3: led_3 {
-			gpios = <&gpio_led0 3>;
-			label = "USERLED3";
-		};
-		led_4: led_4 {
-			gpios = <&gpio_led0 4>;
-			label = "USERLED4";
-		};
-		led_5: led_5 {
-			gpios = <&gpio_led0 5>;
-			label = "USERLED5";
-		};
-		led_6: led_6 {
-			gpios = <&gpio_led0 6>;
-			label = "USERLED6";
-		};
-		led_7: led_7 {
-			gpios = <&gpio_led0 7>;
-			label = "USERLED7";
-		};
-		led_8: led_8 {
-			gpios = <&gpio_led0 8>;
-			label = "PB1LED";
-		};
-		led_9: led_9 {
-			gpios = <&gpio_led0 9>;
-			label = "PB2LED";
-		};
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		user_button_0: button_0 {
-			label = "USERPB0";
-			gpios = <&gpio_button 0>;
-			zephyr,code = <INPUT_KEY_0>;
-		};
-		user_button_1: button_1 {
-			label = "USERPB1";
-			gpios = <&gpio_button 1>;
-			zephyr,code = <INPUT_KEY_1>;
-		};
-	};
-
-	ethosu {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		interrupt-parent = <&nvic>;
-
-		ethosu0: ethosu@48102000 {
-			compatible = "arm,ethos-u";
-			reg = <0x48102000>;
-			interrupts = <56 3>;
-			secure-enable;
-			privilege-enable;
-			status = "okay";
-		};
-	};
-
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -122,6 +43,21 @@
 		};
 	};
 
+	ethosu {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupt-parent = <&nvic>;
+
+		ethosu0: ethosu@48102000 {
+			compatible = "arm,ethos-u";
+			reg = <0x48102000>;
+			interrupts = <56 3>;
+			secure-enable;
+			privilege-enable;
+			status = "okay";
+		};
+	};
+
 	/* We utilize the secure addresses, if you subtract 0x10000000
 	 * you'll get the non-secure alias
 	 */
@@ -149,32 +85,13 @@
 		zephyr,memory-region = "ISRAM";
 	};
 
-	/* DDR4 - 2G, alternates non-secure/secure every 256M */
-	ddr4: memory@60000000 {
-		device_type = "memory";
-		compatible = "zephyr,memory-region";
-		reg = <0x60000000 DT_SIZE_M(256)
-		       0x70000000 DT_SIZE_M(256)
-		       0x80000000 DT_SIZE_M(256)
-		       0x90000000 DT_SIZE_M(256)
-		       0xa0000000 DT_SIZE_M(256)
-		       0xb0000000 DT_SIZE_M(256)
-		       0xc0000000 DT_SIZE_M(256)
-		       0xd0000000 DT_SIZE_M(256)>;
-		zephyr,memory-region = "DDR4";
-	};
-
 	soc {
 		peripheral@50000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x0 0x50000000 0x10000000>;
 
-			#include "mps3_an547-common.dtsi"
+			#include "mps3_common_soc_peripheral.dtsi"
 		};
 	};
 };
-
-&nvic {
-	arm,num-irq-priority-bits = <3>;
-};

boards/arm/mps3/mps3_corstone300_an547.yaml

@@ -1,11 +1,12 @@
 #
 # Copyright (c) 2019-2021 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 #
 # SPDX-License-Identifier: Apache-2.0
 #
 
-identifier: mps3/an547
+identifier: mps3/corstone300/an547
-name: Arm MPS3-AN547
+name: Arm MPS3-Corstone300-AN547
 type: mcu
 arch: arm
 ram: 512

boards/arm/mps3/mps3_corstone300_an547_defconfig

@@ -1,5 +1,6 @@
 #
 # Copyright (c) 2018-2021 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 #
 # SPDX-License-Identifier: Apache-2.0
 #

boards/arm/mps3/mps3_corstone300_an547_ns.dts

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018-2021 Linaro Limited
+ * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,19 +11,13 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
+#include "mps3_common.dtsi"
 
 / {
 	compatible = "arm,mps3-an547";
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	aliases {
-		led0 = &led_0;
-		led1 = &led_1;
-		sw0 = &user_button_0;
-		sw1 = &user_button_1;
-	};
-
 	chosen {
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
@@ -30,32 +25,6 @@
 		zephyr,flash = &code;
 	};
 
-	leds {
-		compatible = "gpio-leds";
-		led_0: led_0 {
-			gpios = <&gpio_led0 0>;
-			label = "USERLED0";
-		};
-		led_1: led_1 {
-			gpios = <&gpio_led0 1>;
-			label = "USERLED1";
-		};
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		user_button_0: button_0 {
-			label = "USERPB0";
-			gpios = <&gpio_button 0>;
-			zephyr,code = <INPUT_KEY_0>;
-		};
-		user_button_1: button_1 {
-			label = "USERPB1";
-			gpios = <&gpio_button 1>;
-			zephyr,code = <INPUT_KEY_1>;
-		};
-	};
-
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -101,21 +70,6 @@
 		zephyr,memory-region = "ISRAM";
 	};
 
-	/* DDR4 - 2G, alternates non-secure/secure every 256M */
-	ddr4: memory@60000000 {
-		device_type = "memory";
-		compatible = "zephyr,memory-region";
-		reg = <0x60000000 DT_SIZE_M(256)
-		       0x70000000 DT_SIZE_M(256)
-		       0x80000000 DT_SIZE_M(256)
-		       0x90000000 DT_SIZE_M(256)
-		       0xa0000000 DT_SIZE_M(256)
-		       0xb0000000 DT_SIZE_M(256)
-		       0xc0000000 DT_SIZE_M(256)
-		       0xd0000000 DT_SIZE_M(256)>;
-		zephyr,memory-region = "DDR4";
-	};
-
 	reserved-memory {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -124,15 +78,15 @@
 		/* The memory regions defined below must match what the TF-M
 		 * project has defined for that board - a single image boot is
 		 * assumed. Please see the memory layout in:
-		 * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/an547/partition/flash_layout.h
+		 * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h
 		 */
 
-		code: memory@01060000 {
+		code: memory@28080000 {
-			reg = <0x01060000 DT_SIZE_K(384)>;
+			reg = <0x28080000 DT_SIZE_K(512)>;
 		};
 
-		ram: memory@21000000 {
+		ram: memory@21020000 {
-			reg = <0x21000000 DT_SIZE_M(2)>;
+			reg = <0x21020000 DT_SIZE_M(2)>;
 		};
 	};
 
@@ -142,11 +96,7 @@
 			#size-cells = <1>;
 			ranges = <0x0 0x40000000 0x10000000>;
 
-			#include "mps3_an547-common.dtsi"
+			#include "mps3_common_soc_peripheral.dtsi"
 		};
 	};
 };
-
-&nvic {
-	arm,num-irq-priority-bits = <3>;
-};

boards/arm/mps3/mps3_corstone300_an547_ns.yaml

@@ -1,15 +1,16 @@
 #
 # Copyright (c) 2019-2021 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 #
 # SPDX-License-Identifier: Apache-2.0
 #
 
-identifier: mps3/an547/ns
+identifier: mps3/corstone300/an547/ns
-name: Arm MPS3-AN547_ns
+name: Arm MPS3-Corstone300-AN547_ns
 type: mcu
 arch: arm
 ram: 2048
-flash: 384
+flash: 512
 simulation: qemu
 toolchain:
   - gnuarmemb

boards/arm/mps3/mps3_corstone300_an547_ns_defconfig

@@ -1,5 +1,6 @@
 #
 # Copyright (c) 2018-2021 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 #
 # SPDX-License-Identifier: Apache-2.0
 #

boards/arm/mps3/mps3_corstone300_an552.dts

@@ -0,0 +1,96 @@
+/*
+ * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm/armv8.1-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <mem.h>
+#include "mps3_common.dtsi"
+
+/ {
+	compatible = "arm,mps3-an552";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &dtcm;
+		zephyr,flash = &itcm;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m55";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8.1m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	ethosu {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupt-parent = <&nvic>;
+
+		ethosu0: ethosu@48102000 {
+			compatible = "arm,ethos-u";
+			reg = <0x48102000>;
+			interrupts = <56 3>;
+			secure-enable;
+			privilege-enable;
+			status = "okay";
+		};
+	};
+
+	/* We utilize the secure addresses, if you subtract 0x10000000
+	 * you'll get the non-secure alias
+	 */
+	itcm: itcm@10000000 {	/* alias @ 0x0 */
+		compatible = "zephyr,memory-region";
+		reg = <0x10000000 DT_SIZE_K(512)>;
+		zephyr,memory-region = "ITCM";
+	};
+
+	sram: sram@11000000 {	/* alias @ 0x01000000 */
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x11000000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "SRAM";
+	};
+
+	dtcm: dtcm@30000000 {	/* alias @ 0x20000000 */
+		compatible = "zephyr,memory-region";
+		reg = <0x30000000 DT_SIZE_K(512)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	isram: sram@31000000 {/* alias @ 0x21000000 */
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x31000000 DT_SIZE_M(2)>;
+		zephyr,memory-region = "ISRAM";
+	};
+
+	soc {
+		peripheral@50000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x50000000 0x10000000>;
+
+			#include "mps3_common_soc_peripheral.dtsi"
+		};
+	};
+};

boards/arm/mps3/mps3_corstone300_an552.yaml

@@ -0,0 +1,22 @@
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: mps3/corstone300/an552
+name: Arm MPS3-Corstone300-AN552
+type: mcu
+arch: arm
+ram: 512
+flash: 512
+toolchain:
+  - gnuarmemb
+  - zephyr
+  - xtools
+supported:
+  - gpio
+testing:
+  ignore_tags:
+    - drivers
+    - bluetooth
+    - net
+    - timer
+vendor: arm

boards/arm/mps3/mps3_corstone300_an552_defconfig

@@ -0,0 +1,17 @@
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_RUNTIME_NMI=y
+CONFIG_ARM_TRUSTZONE_M=y
+CONFIG_ARM_MPU=y
+
+# GPIOs
+CONFIG_GPIO=y
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+
+# Build a Secure firmware image
+CONFIG_TRUSTED_EXECUTION_SECURE=y

boards/arm/mps3/mps3_corstone300_an552_ns.dts

@@ -0,0 +1,101 @@
+/*
+ * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm/armv8.1-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <mem.h>
+#include "mps3_common.dtsi"
+
+/ {
+	compatible = "arm,mps3-an552";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &ram;
+		zephyr,flash = &code;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m55";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8.1m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	/* We utilize the secure addresses, if you subtract 0x10000000
+	 * you'll get the non-secure alias
+	 */
+	itcm: itcm@0 {
+		compatible = "zephyr,memory-region";
+		reg = <0x0 DT_SIZE_K(512)>;
+		zephyr,memory-region = "ITCM";
+	};
+
+	sram: sram@1000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x1000000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "SRAM";
+	};
+
+	dtcm: dtcm@20000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x20000000 DT_SIZE_K(512)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	isram: sram@21000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x21000000 DT_SIZE_M(2)>;
+		zephyr,memory-region = "ISRAM";
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* The memory regions defined below must match what the TF-M
+		 * project has defined for that board - a single image boot is
+		 * assumed. Please see the memory layout in:
+		 * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h
+		 */
+
+		code: memory@28080000 {
+			reg = <0x28080000 DT_SIZE_K(512)>;
+		};
+
+		ram: memory@21020000 {
+			reg = <0x21020000 DT_SIZE_M(1)>;
+		};
+	};
+
+	soc {
+		peripheral@40000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x40000000 0x10000000>;
+
+			#include "mps3_common_soc_peripheral.dtsi"
+		};
+	};
+};

boards/arm/mps3/mps3_corstone300_an552_ns.yaml

@@ -0,0 +1,17 @@
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: mps3/corstone300/an552/ns
+name: Arm MPS3-Corstone300-AN552_ns
+type: mcu
+arch: arm
+ram: 2048
+flash: 512
+toolchain:
+  - gnuarmemb
+  - zephyr
+  - xtools
+testing:
+  default: true
+  only_tags:
+    - trusted-firmware-m

boards/arm/mps3/mps3_corstone300_an552_ns_defconfig

@@ -0,0 +1,18 @@
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_RUNTIME_NMI=y
+CONFIG_ARM_TRUSTZONE_M=y
+CONFIG_ARM_MPU=y
+
+# GPIOs
+CONFIG_GPIO=y
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+
+# Build a Non-secure firmware image
+CONFIG_TRUSTED_EXECUTION_SECURE=n
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y

boards/arm/mps3/mps3_corstone300_fvp.dts

@@ -0,0 +1,96 @@
+/*
+ * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm/armv8.1-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <mem.h>
+#include "mps3_common.dtsi"
+
+/ {
+	compatible = "arm,mps3-fvp";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &dtcm;
+		zephyr,flash = &itcm;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m55";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8.1m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	ethosu {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupt-parent = <&nvic>;
+
+		ethosu0: ethosu@48102000 {
+			compatible = "arm,ethos-u";
+			reg = <0x48102000>;
+			interrupts = <56 3>;
+			secure-enable;
+			privilege-enable;
+			status = "okay";
+		};
+	};
+
+	/* We utilize the secure addresses, if you subtract 0x10000000
+	 * you'll get the non-secure alias
+	 */
+	itcm: itcm@10000000 {	/* alias @ 0x0 */
+		compatible = "zephyr,memory-region";
+		reg = <0x10000000 DT_SIZE_K(512)>;
+		zephyr,memory-region = "ITCM";
+	};
+
+	sram: sram@11000000 {	/* alias @ 0x01000000 */
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x11000000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "SRAM";
+	};
+
+	dtcm: dtcm@30000000 {	/* alias @ 0x20000000 */
+		compatible = "zephyr,memory-region";
+		reg = <0x30000000 DT_SIZE_K(512)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	isram: sram@31000000 {/* alias @ 0x21000000 */
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x31000000 DT_SIZE_M(2)>;
+		zephyr,memory-region = "ISRAM";
+	};
+
+	soc {
+		peripheral@50000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x50000000 0x10000000>;
+
+			#include "mps3_common_soc_peripheral.dtsi"
+		};
+	};
+};

boards/arm/mps3/mps3_corstone300_fvp.yaml

@@ -0,0 +1,24 @@
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: mps3/corstone300/fvp
+name: Arm MPS3-Corstone300-FVP
+type: mcu
+arch: arm
+ram: 512
+flash: 512
+simulation: armfvp
+simulation_exec: FVP_Corstone_SSE-300_Ethos-U55
+toolchain:
+  - gnuarmemb
+  - zephyr
+  - xtools
+supported:
+  - gpio
+testing:
+  ignore_tags:
+    - drivers
+    - bluetooth
+    - net
+    - timer
+vendor: arm

boards/arm/mps3/mps3_corstone300_fvp_defconfig

@@ -0,0 +1,17 @@
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_RUNTIME_NMI=y
+CONFIG_ARM_TRUSTZONE_M=y
+CONFIG_ARM_MPU=y
+
+# GPIOs
+CONFIG_GPIO=y
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+
+# Build a Secure firmware image
+CONFIG_TRUSTED_EXECUTION_SECURE=y

boards/arm/mps3/mps3_corstone300_fvp_ns.dts

@@ -0,0 +1,101 @@
+/*
+ * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm/armv8.1-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <mem.h>
+#include "mps3_common.dtsi"
+
+/ {
+	compatible = "arm,mps3-fvp";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &ram;
+		zephyr,flash = &code;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m55";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8.1m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	/* We utilize the secure addresses, if you subtract 0x10000000
+	 * you'll get the non-secure alias
+	 */
+	itcm: itcm@0 {
+		compatible = "zephyr,memory-region";
+		reg = <0x0 DT_SIZE_K(512)>;
+		zephyr,memory-region = "ITCM";
+	};
+
+	sram: sram@1000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x1000000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "SRAM";
+	};
+
+	dtcm: dtcm@20000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x20000000 DT_SIZE_K(512)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	isram: sram@21000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x21000000 DT_SIZE_M(2)>;
+		zephyr,memory-region = "ISRAM";
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* The memory regions defined below must match what the TF-M
+		 * project has defined for that board - a single image boot is
+		 * assumed. Please see the memory layout in:
+		 * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h
+		 */
+
+		code: memory@28080000 {
+			reg = <0x28080000 DT_SIZE_K(512)>;
+		};
+
+		ram: memory@21020000 {
+			reg = <0x21020000 DT_SIZE_M(1)>;
+		};
+	};
+
+	soc {
+		peripheral@40000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x40000000 0x10000000>;
+
+			#include "mps3_common_soc_peripheral.dtsi"
+		};
+	};
+};

boards/arm/mps3/mps3_corstone300_fvp_ns.yaml

@@ -0,0 +1,17 @@
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: mps3/corstone300/fvp/ns
+name: Arm MPS3-Corstone300-FVP_ns
+type: mcu
+arch: arm
+ram: 2048
+flash: 512
+toolchain:
+  - gnuarmemb
+  - zephyr
+  - xtools
+testing:
+  default: true
+  only_tags:
+    - trusted-firmware-m

boards/arm/mps3/mps3_corstone300_fvp_ns_defconfig

@@ -0,0 +1,20 @@
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_RUNTIME_NMI=y
+CONFIG_ARM_TRUSTZONE_M=y
+CONFIG_ARM_MPU=y
+
+# GPIOs
+CONFIG_GPIO=y
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+
+# Build a Non-secure firmware image
+CONFIG_TRUSTED_EXECUTION_SECURE=n
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+CONFIG_BUILD_WITH_TFM=y

boards/deprecated.cmake

@@ -437,10 +437,10 @@ set(mps2_an521_remote_DEPRECATED
     mps2/an521/cpu1
 )
 set(mps3_an547_DEPRECATED
-    mps3
+    mps3/corstone300/547
 )
 set(mps3_an547_ns_DEPRECATED
-    mps3/an547/ns
+    mps3/corstone300/an547/ns
 )
 
 set(native_posix_64_DEPRECATED

doc/releases/release-notes-4.0.rst

@@ -164,6 +164,11 @@ Boards & SoC Support
     with the old name marked as deprecated.
   * PHYTEC: ``mimx8mm_phyboard_polis`` has been renamed to :ref:`phyboard_polis<phyboard_polis>`,
     with the old name marked as deprecated.
+  * The board qualifier for MPS3/AN547 is changed from:
+
+    * ``mps3/an547`` to ``mps3/corstone300/an547`` for secure and
+    * ``mps3/an547/ns`` to ``mps3/corstone300/an547/ns`` for non-secure.
+
 
 * Added support for the following shields:
 

doc/services/tfm/requirements.rst

@@ -10,8 +10,8 @@ The following are some of the boards that can be used with TF-M:
      - NSPE board name
    * - :ref:`mps2_an521_board`
      - ``mps2_an521_ns`` (qemu supported)
-   * - :ref:`mps3_an547_board`
+   * - :ref:`mps3_board`
-     - ``mps3_an547_ns`` (qemu supported)
+     - ``mps3/corstone300/an547/ns`` (qemu supported)
    * - :zephyr:board:`bl5340_dvk`
      - ``bl5340_dvk/nrf5340/cpuapp/ns``
    * - :zephyr:board:`lpcxpresso55s69`

modules/trusted-firmware-m/Kconfig.tfm

@@ -2,6 +2,7 @@
 
 # Copyright (c) 2019, 2020 Linaro Limited
 # Copyright (c) 2020, 2021 Nordic Semiconductor ASA
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 config ZEPHYR_TRUSTED_FIRMWARE_M_MODULE
@@ -11,7 +12,9 @@ config TFM_BOARD
 	string
 	default "nxp/lpcxpresso55s69" if BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS
 	default "arm/mps2/an521" if BOARD_MPS2_AN521_CPU0_NS
-	default "arm/mps3/an547" if BOARD_MPS3_AN547
+	default "arm/mps3/corstone300/fvp"   if BOARD_MPS3_CORSTONE300_FVP_NS
+	default "arm/mps3/corstone300/an547" if BOARD_MPS3_CORSTONE300_AN547_NS
+	default "arm/mps3/corstone300/an552" if BOARD_MPS3_CORSTONE300_AN552_NS
 	default "stm/b_u585i_iot02a" if BOARD_B_U585I_IOT02A
 	default "stm/nucleo_l552ze_q" if BOARD_NUCLEO_L552ZE_Q
 	default "stm/stm32l562e_dk" if BOARD_STM32L562E_DK

samples/modules/tflite-micro/hello_world/README.rst

@@ -65,7 +65,7 @@ the :envvar:`PATH` variable, then building and testing can be done with followin
 commands.
 
 ```
-$ west build -p auto -b mps3/an547 samples/modules/tflite-micro/hello_world/ -T sample.tensorflow.helloworld.cmsis_nn
+$ west build -p auto -b mps3/corstone300/an547 samples/modules/tflite-micro/hello_world/ -T sample.tensorflow.helloworld.cmsis_nn
 $ FVP_Corstone_SSE-300_Ethos-U55 build/zephyr/zephyr.elf
 ```
 

samples/modules/tflite-micro/hello_world/sample.yaml

@@ -23,6 +23,7 @@ tests:
     filter: CONFIG_FULL_LIBC_SUPPORTED
   sample.tensorflow.helloworld.cmsis_nn:
     tags: tensorflow
-    platform_allow: mps3/an547
+    platform_allow:
+      - mps3/corstone300/an547
     extra_configs:
       - CONFIG_TENSORFLOW_LITE_MICRO_CMSIS_NN_KERNELS=y

samples/modules/tflite-micro/tflm_ethosu/README.rst

@@ -43,5 +43,5 @@ commands.
 
 .. code-block:: bash
 
-    $ west build -b mps3/an547 zephyr/samples/modules/tflite-micro/tflm_ethosu
+    $ west build -b mps3/corstone300/an547 zephyr/samples/modules/tflite-micro/tflm_ethosu
     $ FVP_Corstone_SSE-300_Ethos-U55 build/zephyr/zephyr.elf

samples/modules/tflite-micro/tflm_ethosu/sample.yaml

@@ -10,4 +10,4 @@ tests:
     filter: dt_compat_enabled("arm,ethos-u")
     build_only: true
     integration_platforms:
-      - mps3/an547
+      - mps3/corstone300/an547

soc/arm/mps3/Kconfig

@@ -1,11 +1,12 @@
 # Copyright (c) 2017-2021 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_MPS3
 	select ARM
 	select GPIO_MMIO32 if GPIO
 
-config SOC_MPS3_AN547
+config SOC_MPS3_CORSTONE300
 	select CPU_CORTEX_M55
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_ARM_MPU
@@ -17,4 +18,4 @@ config SOC_MPS3_AN547
 
 config ARMV8_1_M_PMU_EVENTCNT
 	int
-	default 8 if SOC_MPS3_AN547
+	default 8 if SOC_MPS3_CORSTONE300

soc/arm/mps3/Kconfig.defconfig.mps3_corstone300

@@ -1,7 +1,8 @@
 # Copyright (c) 2018-2021 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_MPS3_AN547
+if SOC_MPS3_CORSTONE300
 
 config NUM_IRQS
 	default 128

soc/arm/mps3/Kconfig.soc

@@ -1,4 +1,5 @@
 # Copyright (c) 2017-2021 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_MPS3
@@ -10,9 +11,9 @@ config SOC_SERIES_MPS3
 config SOC_SERIES
 	default "mps3" if SOC_SERIES_MPS3
 
-config SOC_MPS3_AN547
+config SOC_MPS3_CORSTONE300
 	bool
 	select SOC_SERIES_MPS3
 
 config SOC
-	default "an547" if SOC_MPS3_AN547
+	default "corstone300" if SOC_MPS3_CORSTONE300

soc/arm/soc.yml

@@ -10,7 +10,7 @@ family:
       - name: cpu1
   - name: mps3
     socs:
-    - name: an547
+    - name: corstone300
   - name: musca
     socs:
     - name: musca_b1

tests/arch/arm/arm_no_multithreading/testcase.yaml

@@ -10,7 +10,7 @@ tests:
       - qemu_cortex_m3
       - mps2/an385
       - mps2/an521/cpu0
-      - mps3/an547
+      - mps3/corstone300/an547
       - nrf52840dk/nrf52840
       - nrf9160dk/nrf9160
       - nrf51dk/nrf51822

tests/arch/arm/arm_thread_swap_tz/testcase.yaml

@@ -9,7 +9,7 @@ tests:
   arch.arm.swap.tz:
     # NOTE: this platform disables FPU access in TFM.
     platform_exclude:
-      - mps3/an547/ns
+      - mps3/corstone300/an547/ns
       - nucleo_l552ze_q/stm32l552xx/ns
     integration_platforms:
       - mps2/an521/cpu0/ns
@@ -18,7 +18,7 @@ tests:
       - CONFIG_ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS=n
     # NOTE: this platform disables FPU access in TFM.
     platform_exclude:
-      - mps3/an547/ns
+      - mps3/corstone300/an547/ns
       - nucleo_l552ze_q/stm32l552xx/ns
     integration_platforms:
       - mps2/an521/cpu0/ns

tests/benchmarks/cmsis_dsp/basicmath/testcase.yaml

@@ -17,7 +17,7 @@ tests:
     filter: CONFIG_CPU_HAS_FPU
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - fpu
     extra_configs:

tests/kernel/mem_protect/mem_protect/testcase.yaml

@@ -24,8 +24,8 @@ tests:
     arch_allow: arm
     platform_allow:
       - slwrb4180a
-      - mps3/an547
+      - mps3/corstone300/an547
       - nrf9160dk/nrf9160
     integration_platforms:
-      - mps3/an547
+      - mps3/corstone300/an547
     extra_args: CONFIG_MPU_GAP_FILLING=y

tests/kernel/mem_protect/userspace/testcase.yaml

@@ -23,8 +23,8 @@ tests:
     arch_allow: arm
     platform_allow:
       - slwrb4180a
-      - mps3/an547
+      - mps3/corstone300/an547
       - nrf9160dk/nrf9160
     integration_platforms:
-      - mps3/an547
+      - mps3/corstone300/an547
     extra_args: CONFIG_MPU_GAP_FILLING=y

tests/lib/cmsis_dsp/bayes/testcase.yaml

@@ -16,7 +16,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu

tests/lib/cmsis_dsp/complexmath/testcase.yaml

@@ -15,7 +15,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu

tests/lib/cmsis_dsp/distance/testcase.yaml

@@ -15,7 +15,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu

tests/lib/cmsis_dsp/fastmath/testcase.yaml

@@ -15,7 +15,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu

tests/lib/cmsis_dsp/filtering/testcase.yaml

@@ -26,7 +26,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -55,7 +55,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -84,7 +84,8 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
+      - mps3/corstone300/an552
     tags:
       - cmsis-dsp
       - fpu
@@ -114,7 +115,8 @@ tests:
     integration_platforms:
       - mps2/an521/cpu1
     platform_exclude:
-      - mps3/an547
+      - mps3/corstone300/an547
+      - mps3/corstone300/an552
     tags:
       - cmsis-dsp
       - fpu

tests/lib/cmsis_dsp/interpolation/testcase.yaml

@@ -15,7 +15,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu

tests/lib/cmsis_dsp/matrix/testcase.yaml

@@ -23,7 +23,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -52,7 +52,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -81,7 +81,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -109,7 +109,7 @@ tests:
       and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED)
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -138,7 +138,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -167,7 +167,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -197,7 +197,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -228,7 +228,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -259,7 +259,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -288,7 +288,7 @@ tests:
       and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED)
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -318,7 +318,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -349,7 +349,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu

tests/lib/cmsis_dsp/quaternionmath/testcase.yaml

@@ -15,7 +15,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu

tests/lib/cmsis_dsp/statistics/testcase.yaml

@@ -16,7 +16,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu

tests/lib/cmsis_dsp/support/testcase.yaml

@@ -15,7 +15,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu

tests/lib/cmsis_dsp/svm/testcase.yaml

@@ -15,7 +15,7 @@ tests:
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu

tests/lib/cmsis_dsp/transform/testcase.yaml

@@ -22,7 +22,7 @@ tests:
     filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -50,7 +50,7 @@ tests:
     filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -129,7 +129,7 @@ tests:
     filter: (CMSIS_DSP_FLOAT16 and (CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M)
       and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED)
     integration_platforms:
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -156,7 +156,7 @@ tests:
     filter: (CMSIS_DSP_FLOAT16 and (CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M)
       and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED)
     integration_platforms:
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu
@@ -210,7 +210,7 @@ tests:
     filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU
       and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - cmsis-dsp
       - fpu

tests/subsys/dsp/basicmath/testcase.yaml

@@ -13,7 +13,7 @@ tests:
     filter: (CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX
     integration_platforms:
       - mps2/an521/cpu1
-      - mps3/an547
+      - mps3/corstone300/an547
     tags:
       - zdsp
       - fpu