Kbuild: Assembly code extension.

This commit set back .S as the assembly code extension for Kbuild.

Change-Id: Ib0119876bd0bed6617bbfbad2ca6a44e172ab042
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>

Makefile

@@ -1102,15 +1102,11 @@ $(help-board-dirs): help-%:
 	$(Q)$(MAKE) $(build)=scripts build_docproc
 	$(Q)$(MAKE) $(build)=Documentation/DocBook $@
 
-
-#BUG [oas] regular expression is substituted by [oa] to ommit the removal
-#    of .s files. This change can be undone once all .s files have been
-#    renamed to .S files.
 clean: $(clean-dirs)
 	$(call cmd,rmdirs)
 	$(call cmd,rmfiles)
 	@find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
-		\( -name '*.[oa]' -o -name '*.ko' -o -name '.*.cmd' \
+		\( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
 		-o -name '*.ko.*' \
 		-o -name '*.dwo'  \
 		-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \

arch/arc/bsp/reset.S

@@ -1,4 +1,4 @@
-/* reset.s - reset handler */
+/* reset.S - reset handler */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.

arch/arc/core/atomic.S

@@ -1,4 +1,4 @@
-/* armAtomic.s - ARC atomic operations library */
+/* armAtomic.S - ARC atomic operations library */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.

arch/arc/core/context_wrapper.S

@@ -1,4 +1,4 @@
-/* ctx_wrapper.s - wrapper for _context_entry */
+/* ctx_wrapper.S - wrapper for _context_entry */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.

arch/arc/core/cpu_idle.S

@@ -1,4 +1,4 @@
-/* cpu_idle.s - CPU power management */
+/* cpu_idle.S - CPU power management */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.

arch/arc/core/fast_irq.S

@@ -1,4 +1,4 @@
-/* fast_irq.s - handling of transitions to-and-from fast IRQs (FIRQ) */
+/* fast_irq.S - handling of transitions to-and-from fast IRQs (FIRQ) */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
@@ -34,7 +34,7 @@
 DESCRIPTION
 This module implements the code for handling entry to and exit from Fast IRQs.
 
-See isr_wrapper.s for details.
+See isr_wrapper.S for details.
 */
 
 #define _ASMLANGUAGE

arch/arc/core/fault_s.S

@@ -1,4 +1,4 @@
-/* fault_s.s - fault handlers for ARCv2 */
+/* fault_s.S - fault handlers for ARCv2 */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.

arch/arc/core/irq_lock.S

@@ -1,4 +1,4 @@
-/* irq_lock.s - interrupt locking */
+/* irq_lock.S - interrupt locking */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.

arch/arc/core/isr_wrapper.S

@@ -1,4 +1,4 @@
-/* isr_wrapper.s - wrapper around ISRs with logic for context switching */
+/* isr_wrapper.S - wrapper around ISRs with logic for context switching */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.

arch/arc/core/regular_irq.S

@@ -1,4 +1,4 @@
-/* regular_irq.s - handling of transitions to-and-from regular IRQs (RIRQ) */
+/* regular_irq.S - handling of transitions to-and-from regular IRQs (RIRQ) */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
@@ -35,7 +35,7 @@ DESCRIPTION
 This module implements the code for handling entry to and exit from regular
 IRQs.
 
-See isr_wrapper.s for details.
+See isr_wrapper.S for details.
 */
 
 #define _ASMLANGUAGE

arch/arc/core/swap.S

@@ -1,4 +1,4 @@
-/* swap.s - thread context switching */
+/* swap.S - thread context switching */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.
@@ -35,7 +35,7 @@ DESCRIPTION
 This module implements the routines necessary for thread context switching
 on ARCv2 CPUs.
 
-See isr_wrapper.s for details.
+See isr_wrapper.S for details.
 */
 
 #define _ASMLANGUAGE

arch/arm/bsp/CortexM/reset.S

@@ -1,4 +1,4 @@
-/* reset_s.s - reset handler */
+/* reset_s.S - reset handler */
 
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.

arch/arm/bsp/CortexM/vector_table.S

@@ -1,4 +1,4 @@
-/* vector_table.s - populated vector table in ROM */
+/* vector_table.S - populated vector table in ROM */
 
 /*
  * Copyright (c) 2013-2015 Wind River Systems, Inc.

arch/arm/core/atomic.S

@@ -1,4 +1,4 @@
-/* armAtomic.s - ARM atomic operations library */
+/* armAtomic.S - ARM atomic operations library */
 
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.

arch/arm/core/basepri.S

@@ -1,4 +1,4 @@
-/* basepri.s - ARM Cortex-M interrupt locking via BASEPRI */
+/* basepri.S - ARM Cortex-M interrupt locking via BASEPRI */
 
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.

arch/arm/core/cpu_idle.S

@@ -1,4 +1,4 @@
-/* cpu_idle.s - ARM CORTEX-M3 power management */
+/* cpu_idle.S - ARM CORTEX-M3 power management */
 
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.

arch/arm/core/exc_exit.S

@@ -1,4 +1,4 @@
-/* exc_exit.s - ARM CORTEX-M3 exception/interrupt exit API */
+/* exc_exit.S - ARM CORTEX-M3 exception/interrupt exit API */
 
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.

arch/arm/core/fault_s.S

@@ -1,4 +1,4 @@
-/* fault_s.s - fault handlers for ARM Cortex-M */
+/* fault_s.S - fault handlers for ARM Cortex-M */
 
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.

arch/arm/core/ffs.S

@@ -1,4 +1,4 @@
-/* ffs.s - ARM find first set assembly routines */
+/* ffs.S - ARM find first set assembly routines */
 
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.

arch/arm/core/gdb_stub.S

@@ -1,4 +1,4 @@
-/* gdb_stub.s - extra work performed upon exception entry/exit for GDB */
+/* gdb_stub.S - extra work performed upon exception entry/exit for GDB */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.

arch/arm/core/isr_wrapper.S

@@ -1,4 +1,4 @@
-/* isr_wrapper.s - ARM CORTEX-M3 wrapper for ISRs with parameter  */
+/* isr_wrapper.S - ARM CORTEX-M3 wrapper for ISRs with parameter  */
 
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.

arch/arm/core/swap.S

@@ -1,4 +1,4 @@
-/* swap.s - thread context switching for ARM Cortex-M */
+/* swap.S - thread context switching for ARM Cortex-M */
 
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.

arch/arm/fsl_frdm_k64f/nmi_on_reset.S

@@ -1,4 +1,4 @@
-/* nmi_on_reset.s - default basic NMI handler before the kernel is up */
+/* nmi_on_reset.S - default basic NMI handler before the kernel is up */
 
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.

arch/arm/fsl_frdm_k64f/wdog.S

@@ -1,4 +1,4 @@
-/* wdog.s - watchdog initialization for fsl_frdm_k64f BSP */
+/* wdog.S - watchdog initialization for fsl_frdm_k64f BSP */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.

arch/arm/ti_lm3s6965/nmi_on_reset.S

@@ -1,4 +1,4 @@
-/* nmi_on_reset.s - default basic NMI handler before the kernel is up */
+/* nmi_on_reset.S - default basic NMI handler before the kernel is up */
 
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.

arch/arm/timer/systick_gdb.S

@@ -1,4 +1,4 @@
-/* systick_gdb.c - ARM systick handler stub for GDB debugging */
+/* systick_gdb.S - ARM systick handler stub for GDB debugging */
 
 /*
  * Copyright (c) 2014-2015 Wind River Systems, Inc.

arch/x86/bsp/cache_s.S

@@ -1,4 +1,4 @@
-/* cache_s.s - cache manipulation */
+/* cache_s.S - cache manipulation */
 
 /*
  * Copyright (c) 2013-2014 Wind River Systems, Inc.

arch/x86/bsp/crt0.S

@@ -1,4 +1,4 @@
-/* crt0.s - crt0 module for the IA-32 boards */
+/* crt0.S - crt0 module for the IA-32 boards */
 
 /*
  * Copyright (c) 2010-2014 Wind River Systems, Inc.

arch/x86/bsp/driver_static_irq_stubs.S

@@ -1,4 +1,4 @@
-/* driver_static_irq_stubs.s - interrupt stubs */
+/* driver_static_irq_stubs.S - interrupt stubs */
 
 /*
  * Copyright (c) 2012-2015, Wind River Systems, Inc.

arch/x86/bsp/i8259Boi.S

@@ -1,4 +1,4 @@
-/* i8259Boi.s - Intel 8259A PIC BOI Handler */
+/* i8259Boi.S - Intel 8259A PIC BOI Handler */
 
 /*
  * Copyright (c) 2013-2015 Wind River Systems, Inc.

arch/x86/core/cpuhalt.S

@@ -1,4 +1,4 @@
-/* cpuhalt.s - CPU power management code for IA-32 */
+/* cpuhalt.S - CPU power management code for IA-32 */
 
 /*
  * Copyright (c) 2011-2014 Wind River Systems, Inc.

arch/x86/core/excstub.S

@@ -1,4 +1,4 @@
-/* excstub.s - exception management support for IA-32 architecture */
+/* excstub.S - exception management support for IA-32 architecture */
 
 /*
  * Copyright (c) 2011-2014 Wind River Systems, Inc.

arch/x86/core/ffs.S

@@ -1,4 +1,4 @@
-/* ffs.s - find first set bit APIs for IA-32 architecture */
+/* ffs.S - find first set bit APIs for IA-32 architecture */
 
 /*
  * Copyright (c) 2011-2014 Wind River Systems, Inc.

arch/x86/core/intboiexit.S

@@ -1,4 +1,4 @@
-/* intboiexit.s - spurious interrupt support for IA-32 architecture */
+/* intboiexit.S - spurious interrupt support for IA-32 architecture */
 
 /*
  * Copyright (c) 2010-2014 Wind River Systems, Inc.

arch/x86/core/intstub.S

@@ -1,4 +1,4 @@
-/* intstub.s - interrupt management support for IA-32 architecture */
+/* intstub.S - interrupt management support for IA-32 architecture */
 
 /*
  * Copyright (c) 2010-2014 Wind River Systems, Inc.

arch/x86/core/msr.S

@@ -1,4 +1,4 @@
-/* msr.s - Utilities to read/write the Model Specific Registers (MSRs) */
+/* msr.S - Utilities to read/write the Model Specific Registers (MSRs) */
 
 /*
  * Copyright (c) 2011-2014 Wind River Systems, Inc.

arch/x86/core/nanoatomic.S

@@ -1,4 +1,4 @@
-/* nanoatomic.s - nanokernel atomic operators for IA-32 */
+/* nanoatomic.S - nanokernel atomic operators for IA-32 */
 
 /*
  * Copyright (c) 2011-2014 Wind River Systems, Inc.

arch/x86/core/nanocontext.c

@@ -264,7 +264,7 @@ static void _NewContextInternal(
 
 __asm__("\t.globl _context_entry\n"
 	"\t.section .text\n"
-	"_ContextEntryWrapper:\n" /* should place this func .s file and use
+	"_ContextEntryWrapper:\n" /* should place this func .S file and use
 				     SECTION_FUNC */
 	"\tmovl $0, (%esp)\n" /* zero initialEFLAGS location */
 	"\tjmp _context_entry\n");

arch/x86/core/swap.S

@@ -1,4 +1,4 @@
-/* swap.s - nanokernel swapper code for IA-32 */
+/* swap.S - nanokernel swapper code for IA-32 */
 
 /*
  * Copyright (c) 2010-2014 Wind River Systems, Inc.

arch/x86/core/unaligned.S

@@ -1,4 +1,4 @@
-/* unaligned.s - utility routines to perform unaligned reads/writes */
+/* unaligned.S - utility routines to perform unaligned reads/writes */
 
 /*
  * Copyright (c) 2011-2014 Wind River Systems, Inc.

doc/doxygen/doxygen_guidelines_files.rst

@@ -3,7 +3,7 @@
 File Header Documentation
 #########################
 
-Every .c, .h and .s file must contain a file header comment at the
+Every .c, .h and .S file must contain a file header comment at the
 beginning of the file. The file header must contain:
 
 #. The filename. Use **@file** for Doxygen to auto-complete the

include/arch/arc/v2/ffs.h

@@ -64,7 +64,7 @@ static ALWAYS_INLINE unsigned int nanoFfsMsb_inline(unsigned int op)
 
 	__asm__ volatile(
 
-		/* see explanation in ffs.s */
+		/* see explanation in ffs.S */
 		"fls.f %0, %1;\n\t"
 		"add.nz %0, %0, 1;\n\t"
 		: "=r"(bit)
@@ -93,7 +93,7 @@ static ALWAYS_INLINE unsigned int nanoFfsLsb_inline(unsigned int op)
 
 	__asm__ volatile(
 
-		/* see explanation in ffs.s */
+		/* see explanation in ffs.S */
 		"ffs.f %0, %1;\n\t"
 		"add.nz %0, %0, 1;\n\t"
 		"mov.z %0, 0;\n\t"

include/arch/arm/CortexM/gdb_stub.h

@@ -1,4 +1,4 @@
-/* gdb_stub.s - extra work performed upon exception entry/exit for GDB */
+/* gdb_stub.h - extra work performed upon exception entry/exit for GDB */
 
 /*
  * Copyright (c) 2014 Wind River Systems, Inc.

samples/microkernel/test/test_static_idt/src/test_stubs.S

@@ -1,4 +1,4 @@
-/* test_stubs.s - Exception and interrupt stubs */
+/* test_stubs.S - Exception and interrupt stubs */
 
 /*
  * Copyright (c) 2012-2014 Wind River Systems, Inc.

scripts/Makefile.build

@@ -292,9 +292,7 @@ $(obj)/%.s: $(src)/%.S FORCE
 quiet_cmd_as_o_S = AS $(quiet_modtag)  $@
 cmd_as_o_S       = $(CC) $(a_flags) -c -o $@ $<
 
-#BUG: Asm files are currently name with the .s extension. They will need to
+$(obj)/%.o: $(src)/%.S FORCE
-#     change their extension names to .S and restore this rule to handle it.
-$(obj)/%.o: $(src)/%.s FORCE
 	$(call if_changed_dep,as_o_S)
 
 targets += $(real-objs-y) $(real-objs-m) $(lib-y)