dts: arm: stm32l4_plus serie definition from stm32l4p5
Change the dtsi order for the stm32L4plus serie, starting with stm32l4p5-stm32l4q5 and stm32l4r5-stm32l4s5 Significant changes are on the SRAM size, the sdmmc2 and separated RTC-bbram registers. Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu
Fabio Baltieri
parent
8d7295adde
commit
306dea6ff3
4 changed files with 429 additions and 376 deletions
400
dts/arm/st/l4/stm32l4p5.dtsi
Normal file
400
dts/arm/st/l4/stm32l4p5.dtsi
Normal file
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@ -0,0 +1,400 @@
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/*
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* Copyright (c) 2018 Pushpal Sidhu
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/l4/stm32l4.dtsi>
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#include <zephyr/dt-bindings/flash_controller/ospi.h>
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/delete-node/ &quadspi;
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(320)>;
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};
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soc {
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clocks {
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clk_hsi48: clk-hsi48 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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status = "disabled";
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};
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};
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flash-controller@40022000 {
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flash0: flash@8000000 {
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erase-block-size = <4096>;
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};
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};
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rcc: rcc@40021000 {
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undershoot-prevention;
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};
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rng: rng@50060800 {
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
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<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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};
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pinctrl: pin-controller@48000000 {
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reg = <0x48000000 0x2400>;
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gpiod: gpio@48000c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
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};
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gpioe: gpio@48001000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
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};
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gpiof: gpio@48001400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
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};
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gpiog: gpio@48001800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
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};
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gpioi: gpio@48002000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48002000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
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};
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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resets = <&rctl STM32_RESET(APB1L, 18U)>;
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interrupts = <39 0>;
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status = "disabled";
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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resets = <&rctl STM32_RESET(APB1L, 19U)>;
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interrupts = <52 0>;
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status = "disabled";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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resets = <&rctl STM32_RESET(APB1L, 20U)>;
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interrupts = <53 0>;
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status = "disabled";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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i2c4: i2c@40008400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40008400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
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interrupts = <84 0>, <83 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <36 5>;
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status = "disabled";
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};
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spi3: spi@40003c00 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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interrupts = <51 5>;
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status = "disabled";
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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resets = <&rctl STM32_RESET(APB1L, 1U)>;
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interrupts = <29 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers4: timers@40000800 {
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compatible = "st,stm32-timers";
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reg = <0x40000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
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resets = <&rctl STM32_RESET(APB1L, 2U)>;
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interrupts = <30 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers5: timers@40000c00 {
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compatible = "st,stm32-timers";
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reg = <0x40000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
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resets = <&rctl STM32_RESET(APB1L, 3U)>;
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interrupts = <50 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers7: timers@40001400 {
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
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resets = <&rctl STM32_RESET(APB1L, 5U)>;
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interrupts = <55 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers8: timers@40013400 {
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compatible = "st,stm32-timers";
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reg = <0x40013400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
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resets = <&rctl STM32_RESET(APB2, 13U)>;
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interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers17: timers@40014800 {
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compatible = "st,stm32-timers";
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reg = <0x40014800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
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resets = <&rctl STM32_RESET(APB2, 18U)>;
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interrupts = <26 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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can1: can@40006400 {
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compatible = "st,stm32-can";
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reg = <0x40006400 0x400>;
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interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
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interrupt-names = "TX", "RX0", "RX1", "SCE";
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN
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status = "disabled";
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sjw = <1>;
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sample-point = <875>;
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};
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aes: aes@50060000 {
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compatible = "st,stm32-aes";
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reg = <0x50060000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
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interrupts = <79 0>;
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interrupt-names = "aes";
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status = "disabled";
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};
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usbotg_fs: otgfs@50000000 {
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compatible = "st,stm32-otgfs";
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reg = <0x50000000 0x40000>;
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interrupts = <67 0>;
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interrupt-names = "otgfs";
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num-bidir-endpoints = <6>;
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ram-size = <1280>;
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maximum-speed = "full-speed";
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00001000>,
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<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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phys = <&otgfs_phy>;
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status = "disabled";
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};
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dma1: dma@40020000 {
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dma-offset = <0>;
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};
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dma2: dma@40020400 {
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dma-offset = <7>;
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};
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dmamux1: dmamux@40020800 {
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compatible = "st,stm32-dmamux";
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#dma-cells = <3>;
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reg = <0x40020800 0x400>;
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interrupts = <94 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
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dma-channels = <14>;
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dma-generators = <4>;
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dma-requests= <89>;
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status = "disabled";
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};
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sdmmc1: sdmmc@50062400 {
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compatible = "st,stm32-sdmmc";
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reg = <0x50062400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x400000>,
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<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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resets = <&rctl STM32_RESET(AHB2, 22U)>;
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interrupts = <49 0>;
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status = "disabled";
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};
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sdmmc2: sdmmc@50062800 {
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compatible = "st,stm32-sdmmc";
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reg = <0x50062800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x800000>,
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<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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resets = <&rctl STM32_RESET(AHB2, 23U)>;
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interrupts = <47 0>;
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status = "disabled";
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};
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dac1: dac@40007400 {
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compatible = "st,stm32-dac";
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reg = <0x40007400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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octospi1: octospi@a0001000 {
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compatible = "st,stm32-ospi";
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reg = <0xa0001000 0x400>;
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interrupts = <71 0>;
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clock-names = "ospix", "ospi-ker", "ospi-mgr";
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clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>,
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<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
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<&rcc STM32_CLOCK_BUS_AHB2 0x00100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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octospi2: octospi@a0001400 {
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compatible = "st,stm32-ospi";
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reg = <0xa0001400 0x400>;
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interrupts = <76 0>;
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clock-names = "ospix", "ospi-ker", "ospi-mgr";
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clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000200>,
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<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
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<&rcc STM32_CLOCK_BUS_AHB2 0x00100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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otgfs_phy: otgfs_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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};
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18
dts/arm/st/l4/stm32l4p5Xi.dtsi
Normal file
18
dts/arm/st/l4/stm32l4p5Xi.dtsi
Normal file
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@ -0,0 +1,18 @@
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/*
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* Copyright (c) 2023 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/l4/stm32l4p5.dtsi>
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/ {
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(1024)>;
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};
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};
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};
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};
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7
dts/arm/st/l4/stm32l4q5.dtsi
Normal file
7
dts/arm/st/l4/stm32l4q5.dtsi
Normal file
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/*
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* Copyright (c) 2023 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/l4/stm32l4p5.dtsi>
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@ -1,14 +1,14 @@
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/*
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* Copyright (c) 2018 Pushpal Sidhu
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* Copyright (c) 2023 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/l4/stm32l4.dtsi>
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#include <zephyr/dt-bindings/flash_controller/ospi.h>
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#include <st/l4/stm32l4p5.dtsi>
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/delete-node/ &quadspi;
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/delete-node/ &sdmmc2;
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/delete-node/ &sram0;
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/ {
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sram0: memory@20000000 {
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@ -16,373 +16,6 @@
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};
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soc {
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clocks {
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clk_hsi48: clk-hsi48 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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status = "disabled";
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};
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};
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|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
erase-block-size = <4096>;
|
||||
};
|
||||
};
|
||||
|
||||
rcc: rcc@40021000 {
|
||||
undershoot-prevention;
|
||||
};
|
||||
|
||||
rng: rng@50060800 {
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
|
||||
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@48000000 {
|
||||
reg = <0x48000000 0x2400>;
|
||||
|
||||
gpiod: gpio@48000c00 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48000c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
|
||||
};
|
||||
|
||||
gpioe: gpio@48001000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48001000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
|
||||
};
|
||||
|
||||
gpiof: gpio@48001400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48001400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
|
||||
};
|
||||
|
||||
gpiog: gpio@48001800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48001800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
|
||||
};
|
||||
|
||||
gpioi: gpio@48002000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48002000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
|
||||
};
|
||||
};
|
||||
|
||||
usart3: serial@40004800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
|
||||
resets = <&rctl STM32_RESET(APB1L, 18U)>;
|
||||
interrupts = <39 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@40004c00 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
|
||||
resets = <&rctl STM32_RESET(APB1L, 19U)>;
|
||||
interrupts = <52 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@40005000 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40005000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
|
||||
resets = <&rctl STM32_RESET(APB1L, 20U)>;
|
||||
interrupts = <53 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@40005800 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
|
||||
interrupts = <33 0>, <34 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@40008400 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40008400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
|
||||
interrupts = <83 0>, <84 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <36 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi3: spi@40003c00 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
|
||||
interrupts = <51 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timers3: timers@40000400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
|
||||
resets = <&rctl STM32_RESET(APB1L, 1U)>;
|
||||
interrupts = <29 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers4: timers@40000800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
|
||||
resets = <&rctl STM32_RESET(APB1L, 2U)>;
|
||||
interrupts = <30 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers5: timers@40000c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
|
||||
resets = <&rctl STM32_RESET(APB1L, 3U)>;
|
||||
interrupts = <50 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers7: timers@40001400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
|
||||
resets = <&rctl STM32_RESET(APB1L, 5U)>;
|
||||
interrupts = <55 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers8: timers@40013400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40013400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
|
||||
resets = <&rctl STM32_RESET(APB2, 13U)>;
|
||||
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers17: timers@40014800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
|
||||
resets = <&rctl STM32_RESET(APB2, 18U)>;
|
||||
interrupts = <26 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
can1: can@40006400 {
|
||||
compatible = "st,stm32-can";
|
||||
reg = <0x40006400 0x400>;
|
||||
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
|
||||
interrupt-names = "TX", "RX0", "RX1", "SCE";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN
|
||||
status = "disabled";
|
||||
sjw = <1>;
|
||||
sample-point = <875>;
|
||||
};
|
||||
|
||||
aes: aes@50060000 {
|
||||
compatible = "st,stm32-aes";
|
||||
reg = <0x50060000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
|
||||
interrupts = <79 0>;
|
||||
interrupt-names = "aes";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg_fs: otgfs@50000000 {
|
||||
compatible = "st,stm32-otgfs";
|
||||
reg = <0x50000000 0x40000>;
|
||||
interrupts = <67 0>;
|
||||
interrupt-names = "otgfs";
|
||||
num-bidir-endpoints = <6>;
|
||||
ram-size = <1280>;
|
||||
maximum-speed = "full-speed";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00001000>,
|
||||
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
|
||||
phys = <&otgfs_phy>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma1: dma@40020000 {
|
||||
dma-offset = <0>;
|
||||
};
|
||||
|
||||
dma2: dma@40020400 {
|
||||
dma-offset = <7>;
|
||||
};
|
||||
|
||||
dmamux1: dmamux@40020800 {
|
||||
compatible = "st,stm32-dmamux";
|
||||
#dma-cells = <3>;
|
||||
reg = <0x40020800 0x400>;
|
||||
interrupts = <94 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
|
||||
dma-channels = <14>;
|
||||
dma-generators = <4>;
|
||||
dma-requests= <89>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc1: sdmmc@50062400 {
|
||||
compatible = "st,stm32-sdmmc";
|
||||
reg = <0x50062400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x400000>,
|
||||
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
|
||||
resets = <&rctl STM32_RESET(AHB2, 22U)>;
|
||||
interrupts = <49 0>;
|
||||
idma;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dac1: dac@40007400 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
||||
status = "disabled";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
octospi1: octospi@a0001000 {
|
||||
compatible = "st,stm32-ospi";
|
||||
reg = <0xa0001000 0x400>;
|
||||
interrupts = <71 0>;
|
||||
clock-names = "ospix", "ospi-ker", "ospi-mgr";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>,
|
||||
<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB2 0x00100000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
octospi2: octospi@a0001400 {
|
||||
compatible = "st,stm32-ospi";
|
||||
reg = <0xa0001400 0x400>;
|
||||
interrupts = <76 0>;
|
||||
clock-names = "ospix", "ospi-ker", "ospi-mgr";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000200>,
|
||||
<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB2 0x00100000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@40002800 {
|
||||
bbram: backup_regs {
|
||||
compatible = "st,stm32-bbram";
|
||||
|
|
@ -391,9 +24,4 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
otgfs_phy: otgfs_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue