dts: arm: renesas: ra: Add support for Renesas RA4E1 soc

Add support for r7fa4e10d2cfm, r7fa4e10d2cne soc

Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>

dts/arm/renesas/ra/ra4/r7fa4e10d2cfm.dtsi

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <arm/renesas/ra/ra4/r7fa4e10x.dtsi>
+
+/ {
+	soc {
+		flash-controller@407e0000 {
+			block-32kb-linear-end = <21>;
+
+			flash0: flash@0 {
+				compatible = "renesas,ra-nv-flash";
+				reg = <0x0 DT_SIZE_K(512)>;
+				write-block-size = <128>;
+				erase-block-size = <8192>;
+				renesas,programming-enable;
+			};
+
+			flash1: flash@8000000 {
+				compatible = "renesas,ra-nv-flash";
+				reg = <0x8000000 DT_SIZE_K(8)>;
+				write-block-size = <4>;
+				erase-block-size = <64>;
+				renesas,programming-enable;
+			};
+		};
+	};
+};

dts/arm/renesas/ra/ra4/r7fa4e10d2cne.dtsi

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <arm/renesas/ra/ra4/r7fa4e10x.dtsi>
+
+/ {
+	soc {
+		flash-controller@407e0000 {
+			block-32kb-linear-end = <21>;
+
+			flash0: flash@0 {
+				compatible = "renesas,ra-nv-flash";
+				reg = <0x0 DT_SIZE_K(512)>;
+				write-block-size = <128>;
+				erase-block-size = <8192>;
+				renesas,programming-enable;
+			};
+
+			flash1: flash@8000000 {
+				compatible = "renesas,ra-nv-flash";
+				reg = <0x8000000 DT_SIZE_K(8)>;
+				write-block-size = <4>;
+				erase-block-size = <64>;
+				renesas,programming-enable;
+			};
+		};
+	};
+};

dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi

@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/delete-node/ &spi1;
+/delete-node/ &agt4;
+/delete-node/ &adc1;
+/delete-node/ &iic1;
+
+/ {
+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(128)>;
+		};
+
+		sci3: sci3@40118300 {
+			compatible = "renesas,ra-sci";
+			reg = <0x40118300 0x100>;
+			clocks = <&pclka MSTPB 28>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <3>;
+				status = "disabled";
+			};
+		};
+
+		sci4: sci4@40118400 {
+			compatible = "renesas,ra-sci";
+			reg = <0x40118400 0x100>;
+			clocks = <&pclka MSTPB 27>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <4>;
+				status = "disabled";
+			};
+		};
+
+		adc@40170000 {
+			channel-count = <9>;
+			channel-available-mask = <0x1381f>;
+		};
+
+		pwm2: pwm2@40169200 {
+			compatible = "renesas,ra-pwm";
+			divider = <RA_PWM_SOURCE_DIV_1>;
+			channel = <RA_PWM_CHANNEL_2>;
+			clocks = <&pclkd MSTPE 29>;
+			reg = <0x40169200 0x100>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		trng: trng {
+			compatible = "renesas,ra-sce9-rng";
+			status = "disabled";
+		};
+	};
+
+	clocks: clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		xtal: clock-main-osc {
+			compatible = "renesas,ra-cgc-external-clock";
+			clock-frequency = <DT_FREQ_M(24)>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		hoco: clock-hoco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(20)>;
+			#clock-cells = <0>;
+		};
+
+		moco: clock-moco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+		};
+
+		loco: clock-loco {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		subclk: clock-subclk {
+			compatible = "renesas,ra-cgc-subclk";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			compatible = "renesas,ra-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL */
+			clocks = <&hoco>;
+			div = <2>;
+			mul = <20 0>;
+			status = "disabled";
+		};
+
+		pll2: pll2 {
+			compatible = "renesas,ra-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL2 */
+			div = <2>;
+			mul = <20 0>;
+			status = "disabled";
+		};
+
+		pclkblock: pclkblock@40084000 {
+			compatible = "renesas,ra-cgc-pclk-block";
+			reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
+			      <0x4008400c 4>, <0x40084010 4>;
+			reg-names = "MSTPA", "MSTPB", "MSTPC",
+				    "MSTPD", "MSTPE";
+			#clock-cells = <0>;
+			clocks = <&pll>;
+			status = "okay";
+
+			iclk: iclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <100000000>;
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclka: pclka {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkb: pclkb {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkc: pclkc {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkd: pclkd {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			fclk: fclk {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			clkout: clkout {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			uclk: uclk {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+		};
+	};
+};
+
+&ioport0 {
+	port-irqs = <&port_irq6 &port_irq7 &port_irq8
+	&port_irq9 &port_irq13>;
+	port-irq-names = "port-irq6",
+			 "port-irq7",
+			 "port-irq8",
+			 "port-irq9",
+			 "port-irq13";
+	port-irq6-pins = <0>;
+	port-irq7-pins = <1>;
+	port-irq8-pins = <2>;
+	port-irq9-pins = <4>;
+	port-irq13-pins = <15>;
+};
+
+&ioport1 {
+	port-irqs = <&port_irq0 &port_irq1 &port_irq2
+	&port_irq3 &port_irq4>;
+	port-irq-names = "port-irq0",
+			 "port-irq1",
+			 "port-irq2",
+			 "port-irq3",
+			 "port-irq4";
+	port-irq0-pins = <5>;
+	port-irq1-pins = <1 4>;
+	port-irq2-pins = <0>;
+	port-irq3-pins = <10>;
+	port-irq4-pins = <11>;
+};
+
+&ioport2 {
+	port-irqs = <&port_irq0 &port_irq1 &port_irq2
+	&port_irq3>;
+	port-irq-names = "port-irq0",
+			 "port-irq1",
+			 "port-irq2",
+			 "port-irq3";
+	port-irq0-pins = <6>;
+	port-irq1-pins = <5>;
+	port-irq2-pins = <13>;
+	port-irq3-pins = <12>;
+};
+
+&ioport3 {
+	port-irqs = <&port_irq5 &port_irq6 &port_irq9>;
+	port-irq-names = "port-irq5",
+			 "port-irq6",
+			 "port-irq9";
+	port-irq5-pins = <2>;
+	port-irq6-pins = <1>;
+	port-irq9-pins = <4>;
+};
+
+&ioport4 {
+	port-irqs = <&port_irq0 &port_irq4 &port_irq5
+	&port_irq6 &port_irq7>;
+	port-irq-names = "port-irq0",
+			 "port-irq4",
+			 "port-irq5",
+			 "port-irq6",
+			 "port-irq7";
+	port-irq0-pins = <0>;
+	port-irq4-pins = <2 11>;
+	port-irq5-pins = <1 10>;
+	port-irq6-pins = <9>;
+	port-irq7-pins = <8>;
+};

dts/bindings/clock/renesas,ra-cgc-pclk.yaml

@@ -8,6 +8,10 @@ compatible: "renesas,ra-cgc-pclk"
 include: [clock-controller.yaml, base.yaml]
 
 properties:
+  clock-frequency:
+    type: int
+    description: clock frequency (Hz)
+
   div:
     type: int
     required: true

soc/renesas/ra/ra4e1/CMakeLists.txt

@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/ra/ra4e1/Kconfig

@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA4E1
+	select ARM
+	select CPU_HAS_ARM_MPU
+	select CPU_CORTEX_M33
+	select HAS_RENESAS_RA_FSP
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+	select CPU_CORTEX_M_HAS_DWT
+	select ARMV8_M_DSP
+	select CPU_HAS_FPU
+	select FPU
+	select HAS_SWO
+	select XIP
+	select SOC_EARLY_INIT_HOOK

soc/renesas/ra/ra4e1/Kconfig.defconfig

@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA4E1
+
+config NUM_IRQS
+	default 96
+
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
+# Set to the minimal size of data which can be written.
+config FLASH_FILL_BUFFER_SIZE
+	default 128
+
+endif # SOC_SERIES_RA4E1

soc/renesas/ra/ra4e1/Kconfig.soc

@@ -0,0 +1,27 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA4E1
+	bool
+	select SOC_FAMILY_RENESAS_RA
+	help
+	  Renesas RA4E1 series
+
+config SOC_R7FA4E10D2CFM
+	bool
+	select SOC_SERIES_RA4E1
+	help
+	  R7FA4E10D2CFM
+
+config SOC_R7FA4E10D2CNE
+	bool
+	select SOC_SERIES_RA4E1
+	help
+	  R7FA4E10D2CNE
+
+config SOC_SERIES
+	default "ra4e1" if SOC_SERIES_RA4E1
+
+config SOC
+	default "r7fa4e10d2cfm" if SOC_R7FA4E10D2CFM
+	default "r7fa4e10d2cne" if SOC_R7FA4E10D2CNE

soc/renesas/ra/ra4e1/sections.ld

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+	/* If DTC is used, put the DTC vector table at the start of SRAM.
+		This avoids memory holes due to 1K alignment required by it. */
+	*(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+	__OPTION_SETTING_OFS_Start = .;
+	KEEP(*(.option_setting_ofs0))
+	. = __OPTION_SETTING_OFS_Start + 0x04;
+	KEEP(*(.option_setting_ofs2))
+	. = __OPTION_SETTING_OFS_Start + 0x10;
+	KEEP(*(.option_setting_dualsel))
+	__OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+	__OPTION_SETTING_SAS_Start = .;
+	KEEP(*(.option_setting_sas))
+	__OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+	__OPTION_SETTING_S_Start = .;
+	KEEP(*(.option_setting_ofs1_sec))
+	. = __OPTION_SETTING_S_Start + 0x04;
+	KEEP(*(.option_setting_ofs3_sec))
+	. = __OPTION_SETTING_S_Start + 0x10;
+	KEEP(*(.option_setting_banksel_sec))
+	. = __OPTION_SETTING_S_Start + 0x40;
+	KEEP(*(.option_setting_bps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x44;
+	KEEP(*(.option_setting_bps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x48;
+	KEEP(*(.option_setting_bps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x4C;
+	KEEP(*(.option_setting_bps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x60;
+	KEEP(*(.option_setting_pbps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x64;
+	KEEP(*(.option_setting_pbps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x68;
+	KEEP(*(.option_setting_pbps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x6C;
+	KEEP(*(.option_setting_pbps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x80;
+	KEEP(*(.option_setting_ofs1_sel))
+	. = __OPTION_SETTING_S_Start + 0x84;
+	KEEP(*(.option_setting_ofs3_sel))
+	. = __OPTION_SETTING_S_Start + 0x90;
+	KEEP(*(.option_setting_banksel_sel))
+	. = __OPTION_SETTING_S_Start + 0xC0;
+	KEEP(*(.option_setting_bps_sel0))
+	. = __OPTION_SETTING_S_Start + 0xC4;
+	KEEP(*(.option_setting_bps_sel1))
+	. = __OPTION_SETTING_S_Start + 0xC8;
+	KEEP(*(.option_setting_bps_sel2))
+	. = __OPTION_SETTING_S_Start + 0xCC;
+	KEEP(*(.option_setting_bps_sel3))
+	__OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF

soc/renesas/ra/ra4e1/soc.c

@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA4E1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/arch/arm/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ */
+void soc_early_init_hook(void)
+{
+	extern volatile uint16_t g_protect_counters[];
+
+	for (uint32_t i = 0; i < 4; i++) {
+		g_protect_counters[i] = 0;
+	}
+
+#if FSP_PRIV_TZ_USE_SECURE_REGS
+	/* Disable protection using PRCR register. */
+	R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+
+	/* Initialize peripherals to secure mode for flat projects */
+	R_PSCU->PSARB = 0;
+	R_PSCU->PSARC = 0;
+	R_PSCU->PSARD = 0;
+	R_PSCU->PSARE = 0;
+
+	R_CPSCU->ICUSARG = 0;
+	R_CPSCU->ICUSARH = 0;
+	R_CPSCU->ICUSARI = 0;
+
+	/* Enable protection using PRCR register. */
+	R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
+#endif
+
+	SystemCoreClock = BSP_MOCO_HZ;
+	g_protect_pfswe_counter = 0;
+}

soc/renesas/ra/ra4e1/soc.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA4E1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA4E1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA4E1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA4E1_SOC_H_ */

soc/renesas/ra/soc.yml

@@ -4,6 +4,10 @@ family:
       - name: ra2a1
         socs:
           - name: r7fa2a1ab3cfm
+      - name: ra4e1
+        socs:
+          - name: r7fa4e10d2cfm
+          - name: r7fa4e10d2cne
       - name: ra4e2
         socs:
           - name: r7fa4e2b93cfm