diff --git a/arch/arm/soc/st_stm32/stm32f4/dts.fixup b/arch/arm/soc/st_stm32/stm32f4/dts.fixup index 49a93d4300d..a01e200f628 100644 --- a/arch/arm/soc/st_stm32/stm32f4/dts.fixup +++ b/arch/arm/soc/st_stm32/stm32f4/dts.fixup @@ -83,11 +83,21 @@ #define FLASH_DEV_BASE_ADDRESS ST_STM32F4_FLASH_CONTROLLER_40023C00_BASE_ADDRESS #define FLASH_DEV_NAME ST_STM32F4_FLASH_CONTROLLER_40023C00_LABEL +#ifdef ST_STM32_OTGFS_50000000_BASE_ADDRESS #define CONFIG_USB_BASE_ADDRESS ST_STM32_OTGFS_50000000_BASE_ADDRESS #define CONFIG_USB_IRQ ST_STM32_OTGFS_50000000_IRQ_OTGFS #define CONFIG_USB_IRQ_PRI ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY #define CONFIG_USB_NUM_BIDIR_ENDPOINTS ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS #define CONFIG_USB_RAM_SIZE ST_STM32_OTGFS_50000000_RAM_SIZE +#endif /* ST_STM32_OTGFS_50000000_BASE_ADDRESS */ + +#ifdef ST_STM32_OTGHS_40040000_BASE_ADDRESS +#define CONFIG_USB_HS_BASE_ADDRESS ST_STM32_OTGHS_40040000_BASE_ADDRESS +#define CONFIG_USB_IRQ ST_STM32_OTGHS_40040000_IRQ_OTGHS +#define CONFIG_USB_IRQ_PRI ST_STM32_OTGHS_40040000_IRQ_OTGHS_PRIORITY +#define CONFIG_USB_NUM_BIDIR_ENDPOINTS ST_STM32_OTGHS_40040000_NUM_BIDIR_ENDPOINTS +#define CONFIG_USB_RAM_SIZE ST_STM32_OTGHS_40040000_RAM_SIZE +#endif /* ST_STM32_OTGHS_40040000_BASE_ADDRESS */ #define CONFIG_PWM_STM32_1_DEV_NAME ST_STM32_PWM_40010000_PWM_LABEL #define CONFIG_PWM_STM32_1_PRESCALER ST_STM32_PWM_40010000_PWM_ST_PRESCALER diff --git a/arch/arm/soc/st_stm32/stm32f7/dts.fixup b/arch/arm/soc/st_stm32/stm32f7/dts.fixup index 88367786194..65ff3033123 100644 --- a/arch/arm/soc/st_stm32/stm32f7/dts.fixup +++ b/arch/arm/soc/st_stm32/stm32f7/dts.fixup @@ -50,10 +50,20 @@ #define CONFIG_UART_STM32_USART_8_NAME ST_STM32_USART_40007800_LABEL #define USART_8_IRQ ST_STM32_USART_40007C00_IRQ_0 +#ifdef ST_STM32_OTGFS_50000000_BASE_ADDRESS #define CONFIG_USB_BASE_ADDRESS ST_STM32_OTGFS_50000000_BASE_ADDRESS #define CONFIG_USB_IRQ ST_STM32_OTGFS_50000000_IRQ_OTGFS #define CONFIG_USB_IRQ_PRI ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY #define CONFIG_USB_NUM_BIDIR_ENDPOINTS ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS #define CONFIG_USB_RAM_SIZE ST_STM32_OTGFS_50000000_RAM_SIZE +#endif /* ST_STM32_OTGFS_50000000_BASE_ADDRESS */ + +#ifdef ST_STM32_OTGHS_40040000_BASE_ADDRESS +#define CONFIG_USB_HS_BASE_ADDRESS ST_STM32_OTGHS_40040000_BASE_ADDRESS +#define CONFIG_USB_IRQ ST_STM32_OTGHS_40040000_IRQ_OTGHS +#define CONFIG_USB_IRQ_PRI ST_STM32_OTGHS_40040000_IRQ_OTGHS_PRIORITY +#define CONFIG_USB_NUM_BIDIR_ENDPOINTS ST_STM32_OTGHS_40040000_NUM_BIDIR_ENDPOINTS +#define CONFIG_USB_RAM_SIZE ST_STM32_OTGHS_40040000_RAM_SIZE +#endif /* ST_STM32_OTGHS_40040000_BASE_ADDRESS */ /* End of SoC Level DTS fixup file */