board: arm: add board support files for mimxrt1170_evk

Add board support files for mimxrt1170_evk

- Add pinmux, dts and doc
- Tested samples: hello_world, philosophers, synchronization,
  basic/blinky, basic/button.

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>

boards/arm/mimxrt1170_evk/CMakeLists.txt

@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2021, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_sources(pinmux.c)

boards/arm/mimxrt1170_evk/Kconfig.board

@@ -0,0 +1,12 @@
+# Copyright (c) 2021, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MIMXRT1170_EVK_CM7
+	bool "NXP MIMXRT1170-EVK CM7"
+	depends on SOC_MIMXRT1176_CM7
+	select SOC_PART_NUMBER_MIMXRT1176DVMAA
+
+config BOARD_MIMXRT1170_EVK_CM4
+	bool "NXP MIMXRT1170-EVK CM4"
+	depends on SOC_MIMXRT1176_CM4
+	select SOC_PART_NUMBER_MIMXRT1176DVMAA

boards/arm/mimxrt1170_evk/Kconfig.defconfig

@@ -0,0 +1,17 @@
+# MIMXRT1170-EVK board
+
+# Copyright (c) 2021, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MIMXRT1170_EVK_CM7 || BOARD_MIMXRT1170_EVK_CM4
+
+config BOARD
+	default "mimxrt1170_evk_cm7" if BOARD_MIMXRT1170_EVK_CM7
+	default "mimxrt1170_evk_cm4" if BOARD_MIMXRT1170_EVK_CM4
+
+choice CODE_LOCATION
+	default CODE_FLEXSPI if BOARD_MIMXRT1170_EVK_CM7
+	default CODE_SRAM0 if BOARD_MIMXRT1170_EVK_CM4
+endchoice
+
+endif # BOARD_MIMXRT1170_EVK_CM7 || BOARD_MIMXRT1170_EVK_CM4

boards/arm/mimxrt1170_evk/board.cmake

@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2021, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_runner_args(pyocd "--target=mimxrt1170_cm7")
+board_runner_args(jlink "--device=MIMXRT1176xxxA_M7" "--reset-after-load")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

boards/arm/mimxrt1170_evk/doc/index.rst

@@ -0,0 +1,233 @@
+.. _mimxrt1170_evk:
+
+NXP MIMXRT1170-EVK
+##################
+
+Overview
+********
+
+The dual core i.MX RT1170 runs on the Cortex-M7 core at 1 GHz and on the Cortex-M4
+at 400 MHz. The i.MX RT1170 MCU offers support over a wide temperature range
+and is qualified for consumer, industrial and automotive markets.
+
+.. image:: ./mimxrt1170_evk.jpg
+   :width: 600px
+   :align: center
+   :alt: MIMXRT1170-EVK
+
+Hardware
+********
+
+- MIMXRT1176DVMAA MCU
+
+  - 1GHz Cortex-M7 & 400Mhz Cortex-M4
+  - 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4
+
+- Memory
+
+  - 512 Mbit SDRAM
+  - 128 Mbit QSPI Flash
+  - 512 Mbit Octal Flash
+  - 2 Gbit raw NAND flash
+  - 64 Mbit LPSPI flash
+  - TF socket for SD card
+
+- Display
+
+  - MIPI LCD connector
+
+- Ethernet
+
+  - 10/100 Mbit/s Ethernet PHY
+  - 10/100/1000 Mbit/s Ethernet PHY
+
+- USB
+
+  - USB 2.0 OTG connector
+  - USB 2.0 host connector
+
+- Audio
+
+  - 3.5 mm audio stereo headphone jack
+  - Board-mounted microphone
+  - Left and right speaker out connectors
+
+- Power
+
+  - 5 V DC jack
+
+- Debug
+
+  - JTAG 20-pin connector
+  - OpenSDA with DAPLink
+
+- Sensor
+
+  - FXOS8700CQ 6-axis e-compass
+  - MIPI camera sensor connector
+
+- Expansion port
+
+  - Arduino interface
+
+- CAN bus connector
+
+For more information about the MIMXRT1170 SoC and MIMXRT1170-EVK board, see
+these references:
+
+- `i.MX RT1170 Website`_
+- `i.MX RT1170 Datasheet`_
+- `i.MX RT1170 Reference Manual`_
+- `MIMXRT1170-EVK Website`_
+- `MIMXRT1170-EVK Board Hardware User's Guide`_
+
+Supported Features
+==================
+
+The mimxrt1170_evk board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | systick                             |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+
+The default configuration can be found in the defconfig file:
+``boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig``
+
+Other hardware features are not currently supported by the port.
+
+Connections and I/Os
+====================
+
+The MIMXRT1170 SoC has four pairs of pinmux/gpio controllers.
+
++---------------+-----------------+---------------------------+
+| Name          | Function        | Usage                     |
++===============+=================+===========================+
+| WAKEUP        | GPIO            | SW7                       |
++---------------+-----------------+---------------------------+
+| GPIO_AD_04    | GPIO            | LED                       |
++---------------+-----------------+---------------------------+
+| GPIO_AD_24    | LPUART1_TX      | UART Console              |
++---------------+-----------------+---------------------------+
+| GPIO_AD_25    | LPUART1_RX      | UART Console              |
++---------------+-----------------+---------------------------+
+
+
+System Clock
+============
+
+The MIMXRT1170 SoC is configured to use the 24 MHz external oscillator on the
+board with the on-chip PLL to generate a 1 GHz core clock.
+
+Serial Port
+===========
+
+The MIMXRT1170 SoC has 12 UARTs. One is configured for the console and the
+remaining are not used.
+
+Programming and Debugging
+*************************
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`,
+however the :ref:`pyocd-debug-host-tools` do not yet support programming the
+external flashes on this board so you must reconfigure the board for one of the
+following debug probes instead.
+
+:ref:`jlink-external-debug-probe`
+---------------------------------
+
+Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
+path.
+
+Attach a J-Link 20-pin connector to J1. Check that jumpers J6 and J7
+are **off** (they are on by default when boards ship from the factory) to
+ensure SWD signals are disconnected from the OpenSDA microcontroller.
+
+Configuring a Console
+=====================
+
+Regardless of your choice in debug probe, we will use the OpenSDA
+microcontroller as a usb-to-serial adapter for the serial console. Check that
+jumpers J5 and J8 are **on** (they are on by default when boards ship from
+the factory) to connect UART signals to the OpenSDA microcontroller.
+
+Connect a USB cable from your PC to J11.
+
+Use the following settings with your serial terminal of choice (minicom, putty,
+etc.):
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :ref:`hello_world` application.
+
+Before power on the board, make sure SW1 is set to 0001b
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mimxrt1170_evk_cm7
+   :goals: flash
+
+Power off the board, and change SW1 to 0010b. Then power on the board and
+open a serial terminal, reset the board (press the SW4 button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS v2.4.0-xxxx-xxxxxxxxxxxxx *****
+   Hello World! mimxrt1170_evk_cm7
+
+Debugging
+=========
+
+Here is an example for the :ref:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mimxrt1170_evk_cm7
+   :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS v2.4.0-xxxx-xxxxxxxxxxxxx *****
+   Hello World! mimxrt1170_evk_cm7
+
+.. _MIMXRT1170-EVK Website:
+   https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVK
+
+.. _MIMXRT1170-EVK Board Hardware User's Guide:
+   https://www.nxp.com/webapp/Download?colCode=MIMXRT1170EVKHUG
+
+.. _i.MX RT1170 Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1170-crossover-mcu-family-first-ghz-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1170
+
+.. _i.MX RT1170 Datasheet:
+   https://www.nxp.com/docs/en/data-sheet/IMXRT1170CEC.pdf
+
+.. _i.MX RT1170 Reference Manual:
+   https://www.nxp.com/webapp/Download?colCode=IMXRT1170RM

boards/arm/mimxrt1170_evk/mimxrt1170_evk.dtsi

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		led0 = &green_led;
+		sw0 = &user_button;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		green_led: led-1 {
+			gpios = <&gpio9 3 GPIO_ACTIVE_LOW>;
+			label = "User LED D6";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button: button-1 {
+			label = "User SW7";
+			gpios = <&gpio13 0 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&lpuart1 {
+	status = "okay";
+	current-speed = <115200>;
+};
+
+&user_button {
+	status = "okay";
+};
+
+&green_led {
+	status = "okay";
+};

boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.dts

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_rt1170_cm4.dtsi>
+#include "mimxrt1170_evk.dtsi"
+
+/ {
+	model = "NXP MIMXRT1170-EVK board";
+	compatible = "nxp,mimxrt1176";
+
+	chosen {
+		zephyr,sram = &sram1;
+		zephyr,console = &lpuart1;
+		zephyr,shell-uart = &lpuart1;
+		zephyr,can-primary = &flexcan2;
+	};
+
+	sdram0: memory@80000000 {
+		/* Winbond W9825G6KH-5I */
+		device_type = "memory";
+		reg = <0x80000000 DT_SIZE_M(64)>;
+	};
+};
+
+
+&lpuart1 {
+	status = "okay";
+	current-speed = <115200>;
+};

boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.yaml

@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2021, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt1170_evk_cm4
+name: NXP MIMXRT1170-EVK CM4
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+ram: 128
+flash: 128
+supported:
+  - gpio

boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4_defconfig

@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2021, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SOC_MIMXRT1176_CM4=y
+CONFIG_SOC_SERIES_IMX_RT=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_GPIO=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=400000000
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y

boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_rt1170_cm7.dtsi>
+#include "mimxrt1170_evk.dtsi"
+
+/ {
+	model = "NXP MIMXRT1170-EVK board";
+	compatible = "nxp,mimxrt1176";
+
+	chosen {
+		zephyr,sram = &sdram0;
+		zephyr,console = &lpuart1;
+		zephyr,shell-uart = &lpuart1;
+	};
+
+	sdram0: memory@80000000 {
+		/* Winbond W9825G6KH-5I */
+		device_type = "memory";
+		reg = <0x80000000 DT_SIZE_M(64)>;
+	};
+};
+
+&lpuart1 {
+	status = "okay";
+	current-speed = <115200>;
+};
+
+&flexspi1 {
+	reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>;
+	is25wp128: is25wp128@0 {
+		compatible = "issi,is25wp128", "jedec,spi-nor";
+		size = <134217728>;
+		label = "IS25WP128";
+		reg = <0>;
+		spi-max-frequency = <133000000>;
+		status = "okay";
+		jedec-id = [9d 70 17];
+	};
+};

boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.yaml

@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2021, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt1170_evk_cm7
+name: NXP MIMXRT1170-EVK CM7
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+ram: 256
+flash: 16384
+supported:
+  - gpio

boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig

@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2021, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SOC_MIMXRT1176_CM7=y
+CONFIG_SOC_SERIES_IMX_RT=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_GPIO=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=996000000
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400

boards/arm/mimxrt1170_evk/pinmux.c

@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2021, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+#include <fsl_iomuxc.h>
+#include <fsl_gpio.h>
+#include <soc.h>
+#include <logging/log.h>
+
+LOG_MODULE_REGISTER(mimxrt1170_evk, LOG_LEVEL_INF);
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
+static gpio_pin_config_t enet_gpio_config = {
+	.direction = kGPIO_DigitalOutput,
+	.outputLogic = 0,
+	.interruptMode = kGPIO_NoIntmode
+};
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(csi), okay) && CONFIG_VIDEO
+static  gpio_pin_config_t cam_rst_config = {
+	.direction = kGPIO_DigitalOutput,
+	.outputLogic = 0U,
+	.interruptMode = kGPIO_NoIntmode
+};
+
+static gpio_pin_config_t cam_pwdn_config = {
+	.direction = kGPIO_DigitalOutput,
+	.outputLogic = 0U,
+	.interruptMode = kGPIO_NoIntmode
+};
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
+
+/*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
+ *Speed Field: medium(100MHz)
+ *Open Drain Enable Field: Open Drain Disabled
+ *Pull / Keep Enable Field: Pull/Keeper Enabled
+ *Pull / Keep Select Field: Pull
+ *Pull Up / Down Config. Field: 47K Ohm Pull Up
+ *Hyst. Enable Field: Hysteresis Enabled.
+ */
+
+static void mimxrt1170_evk_usdhc_pinmux(uint16_t nusdhc, bool init,
+		uint32_t speed, uint32_t strength)
+{
+	uint32_t cmd_data = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) |
+			 IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+			 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
+			 IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+			 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
+			 IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+			 IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
+
+	uint32_t clk = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) |
+			IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+			IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
+			IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
+			IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
+
+	if (nusdhc != 0) {
+		LOG_ERR("Invalid USDHC index");
+		return;
+	}
+
+	if (init) {
+		IOMUXC_SetPinMux(IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31, 0U);
+		IOMUXC_SetPinMux(IOMUXC_GPIO_AD_34_USDHC1_VSELECT, 0U);
+		IOMUXC_SetPinMux(IOMUXC_GPIO_AD_35_GPIO10_IO02, 0U);
+		IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_USDHC1_CMD, 1U);
+		IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_USDHC1_CLK, 1U);
+		IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0, 1U);
+		IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1, 1U);
+		IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2, 1U);
+		IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3, 1U);
+		IOMUXC_GPR->GPR43 = ((IOMUXC_GPR->GPR43
+			& (~(IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK)))
+			| IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(0x8000U));
+	}
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC1_CMD, cmd_data);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC1_CLK, clk);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0, cmd_data);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1, cmd_data);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2, cmd_data);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3, cmd_data);
+}
+#endif
+
+static int mimxrt1170_evk_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+	/* USER_LED_CTRL1 */
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_04_GPIO9_IO03, 0U);
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL
+	/* LPUART1 TX/RX */
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_24_LPUART1_TXD, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_25_LPUART1_RXD, 0U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_24_LPUART1_TXD, 0x02U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_25_LPUART1_RXD, 0x02U);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(lcdif), okay) && CONFIG_DISPLAY
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_GPIO9_IO01, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_30_GPIO9_IO29, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16, 0U);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) && CONFIG_I2C
+	/* LPI2C1 SCL, SDA */
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_08_LPI2C1_SCL, 1U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_09_LPI2C1_SDA, 1U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_08_LPI2C1_SCL, 0x10U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_09_LPI2C1_SDA, 0x10U);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_32_ENET_MDC, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_33_ENET_MDIO, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK1, 1U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 1U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 1U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, 0U);
+	IOMUXC_GPR->GPR4 = ((IOMUXC_GPR->GPR4 &
+		(~(IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK))) |
+			IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U));
+	IOMUXC_SetPinMux(IOMUXC_GPIO_LPSR_12_GPIO12_IO12, 0U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_12_GPIO9_IO11, 0x06U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0x02U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0x02U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0x02U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK1, 0x02U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 0x06U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 0x06U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0x06U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, 0x06U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_LPSR_12_GPIO12_IO12, 0x0EU);
+
+	/* Initialize ENET_INT GPIO */
+	GPIO_PinInit(GPIO9, 11, &enet_gpio_config);
+	GPIO_PinInit(GPIO12, 12, &enet_gpio_config);
+
+	/* pull up the ENET_INT before RESET. */
+	GPIO_WritePinOutput(GPIO1, 11, 1);
+	GPIO_WritePinOutput(GPIO1, 12, 0);
+
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexpwm1_pwm2), okay) && CONFIG_PWM
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A, 0U);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(csi), okay) && CONFIG_VIDEO
+	/* Initialize GPIO functionality on GPIO_AD_26 (pin L14) */
+	GPIO_PinInit(GPIO9, 25U, &cam_pwdn_config);
+	/* Initialize GPIO functionality on GPIO_DISP_B2_14 (pin A7) */
+	GPIO_PinInit(GPIO11, 15U, &cam_rst_config);
+
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_26_GPIO9_IO25, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_LPSR_06_LPI2C6_SDA, 1U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_LPSR_07_LPI2C6_SCL, 1U);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan3), okay) && CONFIG_CAN
+	IOMUXC_SetPinMux(IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX, 1U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX, 1U);
+
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX, 0x02U);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX, 0x02U);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
+	mimxrt1170_evk_usdhc_pinmux(0, true, 2, 1);
+	imxrt_usdhc_pinmux_cb_register(mimxrt1170_evk_usdhc_pinmux);
+#endif
+
+	return 0;
+}
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
+static int mimxrt1170_evk_phy_reset(const struct device *dev)
+{
+	/* RESET PHY chip. */
+	k_busy_wait(USEC_PER_MSEC * 10U);
+	GPIO_WritePinOutput(GPIO12, 12, 1);
+
+	return 0;
+}
+#endif
+
+SYS_INIT(mimxrt1170_evk_init, PRE_KERNEL_1, 0);
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
+SYS_INIT(mimxrt1170_evk_phy_reset, PRE_KERNEL_2, 0);
+#endif