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tests/drivers/clock_control: Add tests for stm32wba_core

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Add tests to validate implementation of stm32wba clock_control driver.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
This commit is contained in:
Erwan Gouriou 2022-06-22 17:32:46 +02:00 • committed by Carles Cufí
commit 30061ecd7f
11 changed files with 303 additions and 0 deletions
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9
tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/CMakeLists.txt Normal file
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# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.20.0)
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(stm32_clock_configuration_wba)
FILE(GLOB app_sources src/*.c)
target_sources(app PRIVATE ${app_sources})

43
tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/clear_clocks.overlay Normal file
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/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay clears clocks back to a state equivalent to what could
* be found in stm32wba.dtsi
*/
&clk_hse {
status = "disabled";
/delete-property/ hse-div;
};
&clk_hsi {
status = "disabled";
};
&clk_lse {
status = "disabled";
};
&pll1 {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&rcc {
/delete-property/ clocks;
/delete-property/ clock-frequency;
/delete-property/ ahb-prescaler;
/delete-property/ ahb5-prescaler;
/delete-property/ ahb-div;
/delete-property/ apb1-prescaler;
/delete-property/ apb2-prescaler;
/delete-property/ apb7-prescaler;
};

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tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/hse_16.overlay Normal file
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/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
status = "okay";
hse-div2;
};
&rcc {
clocks = <&clk_hse>;
clock-frequency = <DT_FREQ_M(16)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb7-prescaler = <1>;
};

24
tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/hse_32.overlay Normal file
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/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
status = "okay";
};
&rcc {
clocks = <&clk_hse>;
clock-frequency = <DT_FREQ_M(32)>;
ahb-prescaler = <1>;
ahb5-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb7-prescaler = <1>;
};

23
tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/hsi_16.overlay Normal file
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/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
status = "okay";
};
&rcc {
clocks = <&clk_hsi>;
clock-frequency = <DT_FREQ_M(16)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb7-prescaler = <1>;
};

24
tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/hsi_16_ahb5_div.overlay Normal file
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/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
status = "okay";
};
&rcc {
clocks = <&clk_hsi>;
clock-frequency = <DT_FREQ_M(16)>;
ahb-prescaler = <1>;
ahb5-div;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb7-prescaler = <1>;
};

34
tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100.overlay Normal file
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/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
status = "okay";
clock-frequency = <DT_FREQ_M(32)>;
};
&pll1 {
div-m = <8>;
mul-n = <100>;
div-q = <2>;
div-r = <4>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(100)>;
ahb-prescaler = <1>;
ahb5-prescaler = <4>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb7-prescaler = <1>;
};

34
tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100_ahb_50.overlay Normal file
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/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
status = "okay";
clock-frequency = <DT_FREQ_M(32)>;
};
&pll1 {
div-m = <8>;
mul-n = <100>;
div-q = <2>;
div-r = <4>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
ahb-prescaler = <2>;
clock-frequency = <DT_FREQ_M(50)>;
ahb5-prescaler = <4>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb7-prescaler = <1>;
};

2
tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/prj.conf Normal file
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CONFIG_ZTEST=y
CONFIG_ZTEST_NEW_API=y

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tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/src/test_stm32_clock_configuration.c Normal file
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/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/ztest.h>
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(test);
ZTEST(stm32_syclck_config, test_hclk_freq)
{
uint32_t soc_hclk_freq;
soc_hclk_freq = HAL_RCC_GetHCLKFreq();
zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_hclk_freq,
"Expected hclk_freq: %d. Actual hclk_freq: %d",
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_hclk_freq);
}
ZTEST(stm32_syclck_config, test_sysclk_src)
{
int sys_clk_src = __HAL_RCC_GET_SYSCLK_SOURCE();
#if STM32_SYSCLK_SRC_PLL
zassert_equal(RCC_SYSCLKSOURCE_STATUS_PLLCLK, sys_clk_src,
"Expected sysclk src: PLL1. Actual sysclk src: %d",
sys_clk_src);
#elif STM32_SYSCLK_SRC_HSE
zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSE, sys_clk_src,
"Expected sysclk src: HSE. Actual sysclk src: %d",
sys_clk_src);
#elif STM32_SYSCLK_SRC_HSI
zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSI, sys_clk_src,
"Expected sysclk src: HSI. Actual sysclk src: %d",
sys_clk_src);
#else
/* Case not expected */
zassert_true((STM32_SYSCLK_SRC_PLL ||
STM32_SYSCLK_SRC_HSE ||
STM32_SYSCLK_SRC_HSI),
"Not expected. sys_clk_src: %d\n", sys_clk_src);
#endif
}
ZTEST(stm32_syclck_config, test_pll_src)
{
uint32_t pll_src = __HAL_RCC_GET_PLL1_OSCSOURCE();
#if STM32_PLL_SRC_HSE
zassert_equal(RCC_PLLSOURCE_HSE, pll_src,
"Expected PLL src: HSE. Actual PLL src: %d",
pll_src);
#elif STM32_PLL_SRC_HSI
zassert_equal(RCC_PLLSOURCE_HSI, pll_src,
"Expected PLL src: HSI. Actual PLL src: %d",
pll_src);
#else
zassert_equal(RCC_PLLSOURCE_NONE, pll_src,
"Expected PLL src: None. Actual PLL src: %d",
pll_src);
#endif
}
ZTEST_SUITE(stm32_syclck_config, NULL, NULL, NULL, NULL, NULL);

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tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/testcase.yaml Normal file
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common:
timeout: 5
platform_allow: nucleo_wba52cg
tests:
drivers.stm32_clock_configuration.wba.sysclksrc_hsi_32:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
drivers.stm32_clock_configuration.wba.sysclksrc_hsi_32_ahb5_div:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16_ahb5_div.overlay"
drivers.stm32_clock_configuration.wba.sysclksrc_hse_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_16.overlay"
drivers.stm32_clock_configuration.wba.sysclksrc_hse_32:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_32.overlay"
drivers.stm32_clock_configuration.wba.sysclksrc_pll_hse_100:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_100.overlay"
drivers.stm32_clock_configuration.wba.sysclksrc_pll_hse_50:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_100_ahb_50.overlay"