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drivers: adc: Add threshold_reg_offset to NPCX adc config structure

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ADC threshold control register offset is provided by devicetree, this
change will add this property into `adc_npcx_config` structure and
update macro to access register accordingly. Driver behavior is not
meant to be impacted.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
This commit is contained in:
Bernardo Perez Priego 2022-05-03 14:58:19 -07:00 • committed by Carles Cufí
commit 2fc78a9b39
2 changed files with 19 additions and 12 deletions
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25
drivers/adc/adc_npcx.c
View file

@ -41,6 +41,8 @@ LOG_MODULE_REGISTER(adc_npcx, CONFIG_ADC_LOG_LEVEL);
#define ADC_NPCX_THRVAL_RESOLUTION 10 #define ADC_NPCX_THRVAL_RESOLUTION 10
#define ADC_NPCX_THRVAL_MAX BIT_MASK(ADC_NPCX_THRVAL_RESOLUTION) #define ADC_NPCX_THRVAL_MAX BIT_MASK(ADC_NPCX_THRVAL_RESOLUTION)
#define THRCTL(dev, ctl_no) (*((volatile uint16_t *) npcx_thrctl_reg(dev, ctl_no)))
/* Device config */ /* Device config */
struct adc_npcx_config { struct adc_npcx_config {
/* adc controller base address */ /* adc controller base address */
@ -51,6 +53,8 @@ struct adc_npcx_config {
const struct npcx_alt *alts_list; const struct npcx_alt *alts_list;
/* amount of thresholds supported */ /* amount of thresholds supported */
const uint8_t threshold_count; const uint8_t threshold_count;
/* threshold control register offset */
const uint16_t threshold_reg_offset;
}; };
struct adc_npcx_threshold_control { struct adc_npcx_threshold_control {
@ -119,6 +123,14 @@ struct adc_npcx_data {
#define HAL_INSTANCE(dev) ((struct adc_reg *)((const struct adc_npcx_config *)(dev)->config)->base) #define HAL_INSTANCE(dev) ((struct adc_reg *)((const struct adc_npcx_config *)(dev)->config)->base)
/* ADC local functions */ /* ADC local functions */
static inline uint32_t npcx_thrctl_reg(const struct device *dev,
uint32_t ctl_no)
{
const struct adc_npcx_config *config = dev->config;
return (config->base + config->threshold_reg_offset) + (ctl_no - 1) * 2;
}
static void adc_npcx_isr(const struct device *dev) static void adc_npcx_isr(const struct device *dev)
{ {
const struct adc_npcx_config *config = dev->config; const struct adc_npcx_config *config = dev->config;
@ -509,16 +521,16 @@ static int adc_npcx_threshold_ctrl_setup(const struct device *dev,
return -EINVAL; return -EINVAL;
} }
SET_FIELD(THRCTL(config->base, (th_sel + 1)), SET_FIELD(THRCTL(dev, (th_sel + 1)),
NPCX_THRCTL_CHNSEL, t_ctrl->chnsel); NPCX_THRCTL_CHNSEL, t_ctrl->chnsel);
if (t_ctrl->l_h) { if (t_ctrl->l_h) {
THRCTL(config->base, (th_sel + 1)) |= BIT(NPCX_THRCTL_L_H); THRCTL(dev, (th_sel + 1)) |= BIT(NPCX_THRCTL_L_H);
} else { } else {
THRCTL(config->base, (th_sel + 1)) &= ~BIT(NPCX_THRCTL_L_H); THRCTL(dev, (th_sel + 1)) &= ~BIT(NPCX_THRCTL_L_H);
} }
/* Set the threshold value. */ /* Set the threshold value. */
SET_FIELD(THRCTL(config->base, (th_sel + 1)), NPCX_THRCTL_THRVAL, SET_FIELD(THRCTL(dev, (th_sel + 1)), NPCX_THRCTL_THRVAL,
t_ctrl->thrval); t_ctrl->thrval);
adc_context_release(&data->ctx, 0); adc_context_release(&data->ctx, 0);
@ -557,7 +569,7 @@ static int adc_npcx_threshold_enable_irq(const struct device *dev,
thrcts = inst->THRCTS & ~GENMASK(config->threshold_count - 1, 0); thrcts = inst->THRCTS & ~GENMASK(config->threshold_count - 1, 0);
/* Enable threshold detection */ /* Enable threshold detection */
THRCTL(config->base, (th_sel + 1)) |= BIT(NPCX_THRCTL_THEN); THRCTL(dev, (th_sel + 1)) |= BIT(NPCX_THRCTL_THEN);
/* clear threshold status */ /* clear threshold status */
thrcts |= BIT(th_sel); thrcts |= BIT(th_sel);
@ -605,7 +617,7 @@ int adc_npcx_threshold_disable_irq(const struct device *dev,
inst->THRCTS = thrcts; inst->THRCTS = thrcts;
/* Disable threshold detection */ /* Disable threshold detection */
THRCTL(config->base, (th_sel + 1)) &= ~BIT(NPCX_THRCTL_THEN); THRCTL(dev, (th_sel + 1)) &= ~BIT(NPCX_THRCTL_THEN);
/* Update active threshold */ /* Update active threshold */
t_data->active_thresholds &= ~BIT(th_sel); t_data->active_thresholds &= ~BIT(th_sel);
@ -674,6 +686,7 @@ static const struct adc_npcx_config adc_npcx_cfg_0 = {
.clk_cfg = NPCX_DT_CLK_CFG_ITEM(0), .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
.alts_list = adc_alts, .alts_list = adc_alts,
.threshold_count = DT_INST_PROP(0, threshold_count), .threshold_count = DT_INST_PROP(0, threshold_count),
.threshold_reg_offset = DT_INST_PROP(0, threshold_reg_offset),
}; };
static struct adc_npcx_threshold_data threshold_data_0; static struct adc_npcx_threshold_data threshold_data_0;

6
soc/arm/nuvoton_npcx/common/reg/reg_def.h
View file

@ -508,17 +508,11 @@ struct adc_reg {
volatile uint16_t MEAST; volatile uint16_t MEAST;
}; };
static inline uint32_t npcx_thrctl_offset(uint32_t ctl_no)
{
return DT_PROP(DT_INST(0, nuvoton_npcx_adc), threshold_reg_offset) + (ctl_no - 1) * 2;
}
static inline uint32_t npcx_chndat_offset(uint32_t ch) static inline uint32_t npcx_chndat_offset(uint32_t ch)
{ {
return 0x40 + ch * 2; return 0x40 + ch * 2;
} }
#define THRCTL(base, ctl_no) (*(volatile uint16_t *)((base) + npcx_thrctl_offset(ctl_no)))
#define CHNDAT(base, ch) (*(volatile uint16_t *)((base) + npcx_chndat_offset(ch))) #define CHNDAT(base, ch) (*(volatile uint16_t *)((base) + npcx_chndat_offset(ch)))
/* ADC register fields */ /* ADC register fields */