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soc: arm: st_stm32: Using LL library to implement gpio functions

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The original implementation of gpio functions access registers
directly. Using LL library can add a set of unifying access
functions for all series of stm32 for avoiding accessing low level
code, and improve readability.

Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
This commit is contained in:
Song Qiang 2019-01-08 18:12:04 +08:00 • committed by Kumar Gala
commit 2fb616efbe
27 changed files with 174 additions and 565 deletions
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269
drivers/gpio/gpio_stm32.c
View file

@ -19,15 +19,6 @@
#include "gpio_stm32.h" #include "gpio_stm32.h"
#include "gpio_utils.h" #include "gpio_utils.h"
/* F1 series STM32 use AFIO register to configure interrupt generation
* and pinmux.
*/
#ifdef CONFIG_SOC_SERIES_STM32F1X
#include "afio_registers.h"
#else
#include "syscfg_registers.h"
#endif
/** /**
* @brief Common GPIO driver for STM32 MCUs. * @brief Common GPIO driver for STM32 MCUs.
*/ */
@ -40,7 +31,7 @@ static void gpio_stm32_isr(int line, void *arg)
struct device *dev = arg; struct device *dev = arg;
struct gpio_stm32_data *data = dev->driver_data; struct gpio_stm32_data *data = dev->driver_data;
if (BIT(line) & data->cb_pins) { if ((BIT(line) & data->cb_pins) != 0) {
_gpio_fire_callbacks(&data->cb, dev, BIT(line)); _gpio_fire_callbacks(&data->cb, dev, BIT(line));
} }
} }
@ -75,109 +66,141 @@ const int gpio_stm32_flags_to_conf(int flags, int *pincfg)
return 0; return 0;
} }
/**
* @brief Translate pin to pinval that the LL library needs
*/
static inline u32_t stm32_pinval_get(int pin)
{
u32_t pinval;
#ifdef CONFIG_SOC_SERIES_STM32F1X
pinval = (1 << pin) << GPIO_PIN_MASK_POS;
if (pin < 8) {
pinval |= 1 << pin;
} else {
pinval |= (1 << pin) | 0x04000000;
}
#else
pinval = 1 << pin;
#endif
return pinval;
}
/** /**
* @brief Configure the hardware. * @brief Configure the hardware.
*/ */
int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf) int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf)
{ {
volatile struct stm32_gpio *gpio = GPIO_TypeDef *gpio = (GPIO_TypeDef *)base_addr;
(struct stm32_gpio *)(base_addr);
int pin_ll = stm32_pinval_get(pin);
#ifdef CONFIG_SOC_SERIES_STM32F1X #ifdef CONFIG_SOC_SERIES_STM32F1X
int cnf, mode, mode_io;
int crpin = pin;
/* pins are configured in CRL (0-7) and CRH (8-15)
* registers
*/
volatile u32_t *reg = &gpio->crl;
ARG_UNUSED(altf); ARG_UNUSED(altf);
if (crpin > 7) { u32_t temp = conf & (STM32_MODE_INOUT_MASK << STM32_MODE_INOUT_SHIFT);
reg = &gpio->crh;
crpin -= 8;
}
/* each port is configured by 2 registers: if (temp == STM32_MODE_INPUT) {
* CNFy[1:0]: Port x configuration bits temp = conf & (STM32_CNF_IN_MASK << STM32_CNF_IN_SHIFT);
* MODEy[1:0]: Port x mode bits
*
* memory layout is repeated for every port:
* | CNF | MODE |
* | [0:1] | [0:1] |
*/
mode_io = (conf >> STM32_MODE_INOUT_SHIFT) & STM32_MODE_INOUT_MASK; if (temp == STM32_CNF_IN_ANALOG) {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_ANALOG);
} else if (temp == STM32_CNF_IN_FLOAT) {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_FLOATING);
} else {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_INPUT);
if (mode_io == STM32_MODE_INPUT) { temp = conf & (STM32_PUPD_MASK << STM32_PUPD_SHIFT);
int in_pudpd = conf & (STM32_PUPD_MASK << STM32_PUPD_SHIFT);
/* Pin configured in input mode */ if (temp == STM32_PUPD_PULL_UP) {
/* Mode: 00 */ LL_GPIO_SetPinPull(gpio, pin_ll, LL_GPIO_PULL_UP);
mode = mode_io; } else {
/* Configuration values: */ LL_GPIO_SetPinPull(gpio, pin_ll, LL_GPIO_PULL_DOWN);
/* 00: Analog mode */ }
/* 01: Floating input */
/* 10: Pull-up/Pull-Down */
cnf = (conf >> STM32_CNF_IN_SHIFT) & STM32_CNF_IN_MASK;
if (in_pudpd == STM32_PUPD_PULL_UP) {
/* enable pull up */
gpio->odr |= 1 << pin;
} else if (in_pudpd == STM32_PUPD_PULL_DOWN) {
/* or pull down */
gpio->odr &= ~(1 << pin);
} }
} else { } else {
/* Pin configured in output mode */ temp = conf & (STM32_CNF_OUT_1_MASK << STM32_CNF_OUT_1_SHIFT);
int mode_speed = ((conf >> STM32_MODE_OSPEED_SHIFT) &
STM32_MODE_OSPEED_MASK); if (temp == STM32_CNF_GP_OUTPUT) {
/* Mode output possible values */ LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_OUTPUT);
/* 01: Max speed 10MHz (default value) */ } else {
/* 10: Max speed 2MHz */ LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_ALTERNATE);
/* 11: Max speed 50MHz */ }
mode = mode_speed + mode_io;
/* Configuration possible values */ temp = conf & (STM32_CNF_OUT_0_MASK << STM32_CNF_OUT_0_SHIFT);
/* x0: Push-pull */
/* x1: Open-drain */ if (temp == STM32_CNF_PUSH_PULL) {
/* 0x: General Purpose Output */ LL_GPIO_SetPinOutputType(gpio, pin_ll, LL_GPIO_OUTPUT_PUSHPULL);
/* 1x: Alternate Function Output */ } else {
cnf = ((conf >> STM32_CNF_OUT_0_SHIFT) & STM32_CNF_OUT_0_MASK) | LL_GPIO_SetPinOutputType(gpio, pin_ll, LL_GPIO_OUTPUT_OPENDRAIN);
(((conf >> STM32_CNF_OUT_1_SHIFT) & STM32_CNF_OUT_1_MASK) }
<< 1);
temp = conf & (STM32_MODE_OSPEED_MASK << STM32_MODE_OSPEED_SHIFT);
if (temp == STM32_MODE_OUTPUT_MAX_2) {
LL_GPIO_SetPinSpeed(gpio, pin_ll, LL_GPIO_SPEED_FREQ_LOW);
} else if (temp == STM32_MODE_OUTPUT_MAX_10) {
LL_GPIO_SetPinSpeed(gpio, pin_ll, LL_GPIO_SPEED_FREQ_MEDIUM);
} else {
LL_GPIO_SetPinSpeed(gpio, pin_ll, LL_GPIO_SPEED_FREQ_HIGH);
}
} }
/* clear bits */
*reg &= ~(0xf << (crpin * 4));
/* set bits */
*reg |= (cnf << (crpin * 4 + 2) | mode << (crpin * 4));
#else #else
unsigned int mode, otype, ospeed, pupd; u32_t temp = conf & (STM32_MODER_MASK << STM32_MODER_SHIFT);
unsigned int pin_shift = pin << 1;
unsigned int afr_bank = pin / 8;
unsigned int afr_shift = (pin % 8) << 2;
u32_t scratch;
mode = (conf >> STM32_MODER_SHIFT) & STM32_MODER_MASK; if (temp == STM32_MODER_OUTPUT_MODE) {
otype = (conf >> STM32_OTYPER_SHIFT) & STM32_OTYPER_MASK; LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_OUTPUT);
ospeed = (conf >> STM32_OSPEEDR_SHIFT) & STM32_OSPEEDR_MASK;
pupd = (conf >> STM32_PUPDR_SHIFT) & STM32_PUPDR_MASK;
scratch = gpio->moder & ~(STM32_MODER_MASK << pin_shift); temp = conf & (STM32_OTYPER_MASK << STM32_OTYPER_SHIFT);
gpio->moder = scratch | (mode << pin_shift);
scratch = gpio->ospeedr & ~(STM32_OSPEEDR_MASK << pin_shift); if (temp == STM32_OTYPER_PUSH_PULL) {
gpio->ospeedr = scratch | (ospeed << pin_shift); LL_GPIO_SetPinOutputType(gpio, pin_ll, LL_GPIO_OUTPUT_PUSHPULL);
} else {
LL_GPIO_SetPinOutputType(gpio, pin_ll, LL_GPIO_OUTPUT_OPENDRAIN);
}
scratch = gpio->otyper & ~(STM32_OTYPER_MASK << pin); temp = conf & (STM32_OSPEEDR_MASK << STM32_OSPEEDR_SHIFT);
gpio->otyper = scratch | (otype << pin);
scratch = gpio->pupdr & ~(STM32_PUPDR_MASK << pin_shift); if (temp == STM32_OSPEEDR_LOW_SPEED) {
gpio->pupdr = scratch | (pupd << pin_shift); LL_GPIO_SetPinSpeed(gpio, pin_ll, LL_GPIO_SPEED_FREQ_LOW);
} else if (temp == STM32_OSPEEDR_MEDIUM_SPEED) {
scratch = gpio->afr[afr_bank] & ~(STM32_AFR_MASK << afr_shift); LL_GPIO_SetPinSpeed(gpio, pin_ll, LL_GPIO_SPEED_FREQ_MEDIUM);
gpio->afr[afr_bank] = scratch | (altf << afr_shift); } else if (temp == STM32_OSPEEDR_HIGH_SPEED) {
LL_GPIO_SetPinSpeed(gpio, pin_ll, LL_GPIO_SPEED_FREQ_HIGH);
#if defined(CONFIG_SOC_SERIES_STM32F2X) || defined(CONFIG_SOC_SERIES_STM32F4X) || \
defined(CONFIG_SOC_SERIES_STM32F7X) || defined(CONFIG_SOC_SERIES_STM32L0X) || \
defined(CONFIG_SOC_SERIES_STM32L4X)
} else if (temp == STM32_OSPEEDR_VERY_HIGH_SPEED) {
LL_GPIO_SetPinSpeed(gpio, pin_ll, LL_GPIO_SPEED_FREQ_VERY_HIGH);
#endif #endif
} else {
return -EINVAL;
}
} else if (temp == STM32_MODER_INPUT_MODE) {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_INPUT);
temp = conf & (STM32_PUPDR_MASK << STM32_PUPDR_SHIFT);
if (temp == STM32_PUPDR_PULL_UP) {
LL_GPIO_SetPinPull(gpio, pin_ll, LL_GPIO_PULL_UP);
} else if (temp == STM32_PUPDR_PULL_DOWN) {
LL_GPIO_SetPinPull(gpio, pin_ll, LL_GPIO_PULL_DOWN);
} else {
LL_GPIO_SetPinPull(gpio, pin_ll, LL_GPIO_PULL_NO);
}
} else if (temp == STM32_MODER_ANALOG_MODE) {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_ANALOG);
} else {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_ALTERNATE);
if (pin < 8) {
LL_GPIO_SetAFPin_0_7(gpio, pin_ll, altf);
} else {
LL_GPIO_SetAFPin_8_15(gpio, pin_ll, altf);
}
}
#endif /* CONFIG_SOC_SERIES_STM32F1X */
return 0; return 0;
} }
@ -186,15 +209,6 @@ int gpio_stm32_configure(u32_t *base_addr, int pin, int conf, int altf)
*/ */
const int gpio_stm32_enable_int(int port, int pin) const int gpio_stm32_enable_int(int port, int pin)
{ {
#ifdef CONFIG_SOC_SERIES_STM32F1X
volatile struct stm32_afio *syscfg =
(struct stm32_afio *)AFIO_BASE;
#else
volatile struct stm32_syscfg *syscfg =
(struct stm32_syscfg *)SYSCFG_BASE;
#endif
volatile union syscfg_exticr *exticr;
#if defined(CONFIG_SOC_SERIES_STM32F2X) || \ #if defined(CONFIG_SOC_SERIES_STM32F2X) || \
defined(CONFIG_SOC_SERIES_STM32F3X) || \ defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) || \ defined(CONFIG_SOC_SERIES_STM32F4X) || \
@ -208,20 +222,20 @@ const int gpio_stm32_enable_int(int port, int pin)
/* Enable SYSCFG clock */ /* Enable SYSCFG clock */
clock_control_on(clk, (clock_control_subsys_t *) &pclken); clock_control_on(clk, (clock_control_subsys_t *) &pclken);
#endif #endif
int shift = 0;
if (pin <= 3) { uint32_t line;
exticr = &syscfg->exticr1;
} else if (pin <= 7) { if (pin > 15) {
exticr = &syscfg->exticr2;
} else if (pin <= 11) {
exticr = &syscfg->exticr3;
} else if (pin <= 15) {
exticr = &syscfg->exticr4;
} else {
return -EINVAL; return -EINVAL;
} }
#if defined(CONFIG_SOC_SERIES_STM32L0X) || \
defined(CONFIG_SOC_SERIES_STM32F0X)
line = ((pin % 4 * 4) << 16) | (pin / 4);
#else
line = (0xF << ((pin % 4 * 4) + 16)) | (pin / 4);
#endif
#ifdef CONFIG_SOC_SERIES_STM32L0X #ifdef CONFIG_SOC_SERIES_STM32L0X
/* /*
* Ports F and G are not present on some STM32L0 parts, so * Ports F and G are not present on some STM32L0 parts, so
@ -233,10 +247,11 @@ const int gpio_stm32_enable_int(int port, int pin)
} }
#endif #endif
shift = 4 * (pin % 4); #ifdef CONFIG_SOC_SERIES_STM32F1X
LL_GPIO_AF_SetEXTISource(port, line);
exticr->val &= ~(0xf << shift); #else
exticr->val |= port << shift; LL_SYSCFG_SetEXTISource(port, line);
#endif
return 0; return 0;
} }
@ -259,30 +274,30 @@ static int gpio_stm32_config(struct device *dev, int access_op,
* configuration * configuration
*/ */
map_res = gpio_stm32_flags_to_conf(flags, &pincfg); map_res = gpio_stm32_flags_to_conf(flags, &pincfg);
if (map_res) { if (map_res != 0) {
return map_res; return map_res;
} }
if (gpio_stm32_configure(cfg->base, pin, pincfg, 0)) { if (gpio_stm32_configure(cfg->base, pin, pincfg, 0) != 0) {
return -EIO; return -EIO;
} }
if (flags & GPIO_INT) { if ((flags & GPIO_INT) != 0) {
if (stm32_exti_set_callback(pin, cfg->port, if (stm32_exti_set_callback(pin, cfg->port,
gpio_stm32_isr, dev)) { gpio_stm32_isr, dev) != 0) {
return -EBUSY; return -EBUSY;
} }
gpio_stm32_enable_int(cfg->port, pin); gpio_stm32_enable_int(cfg->port, pin);
if (flags & GPIO_INT_EDGE) { if ((flags & GPIO_INT_EDGE) != 0) {
int edge = 0; int edge = 0;
if (flags & GPIO_INT_DOUBLE_EDGE) { if ((flags & GPIO_INT_DOUBLE_EDGE) != 0) {
edge = STM32_EXTI_TRIG_RISING | edge = STM32_EXTI_TRIG_RISING |
STM32_EXTI_TRIG_FALLING; STM32_EXTI_TRIG_FALLING;
} else if (flags & GPIO_INT_ACTIVE_HIGH) { } else if ((flags & GPIO_INT_ACTIVE_HIGH) != 0) {
edge = STM32_EXTI_TRIG_RISING; edge = STM32_EXTI_TRIG_RISING;
} else { } else {
edge = STM32_EXTI_TRIG_FALLING; edge = STM32_EXTI_TRIG_FALLING;
@ -304,17 +319,17 @@ static int gpio_stm32_write(struct device *dev, int access_op,
u32_t pin, u32_t value) u32_t pin, u32_t value)
{ {
const struct gpio_stm32_config *cfg = dev->config->config_info; const struct gpio_stm32_config *cfg = dev->config->config_info;
struct stm32_gpio *gpio = (struct stm32_gpio *)cfg->base; GPIO_TypeDef *gpio = (GPIO_TypeDef *)cfg->base;
int pval = 1 << (pin & 0xf);
if (access_op != GPIO_ACCESS_BY_PIN) { if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP; return -ENOTSUP;
} }
pin = stm32_pinval_get(pin);
if (value != 0) { if (value != 0) {
gpio->odr |= pval; LL_GPIO_SetOutputPin(gpio, pin);
} else { } else {
gpio->odr &= ~pval; LL_GPIO_ResetOutputPin(gpio, pin);
} }
return 0; return 0;
@ -327,13 +342,13 @@ static int gpio_stm32_read(struct device *dev, int access_op,
u32_t pin, u32_t *value) u32_t pin, u32_t *value)
{ {
const struct gpio_stm32_config *cfg = dev->config->config_info; const struct gpio_stm32_config *cfg = dev->config->config_info;
struct stm32_gpio *gpio = (struct stm32_gpio *)cfg->base; GPIO_TypeDef *gpio = (GPIO_TypeDef *)cfg->base;
if (access_op != GPIO_ACCESS_BY_PIN) { if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP; return -ENOTSUP;
} }
*value = (gpio->idr >> pin) & 0x1; *value = (LL_GPIO_ReadInputPort(gpio) >> pin) & 0x1;
return 0; return 0;
} }

35
drivers/gpio/gpio_stm32.h
View file

@ -139,41 +139,6 @@ struct gpio_stm32_data {
sys_slist_t cb; sys_slist_t cb;
}; };
/**
* @brief layout of stm32 gpio registers
*/
struct stm32_gpio {
#ifdef CONFIG_SOC_SERIES_STM32F1X
u32_t crl;
u32_t crh;
u32_t idr;
u32_t odr;
u32_t bsrr;
u32_t brr;
u32_t lckr;
#else
u32_t moder;
u32_t otyper;
u32_t ospeedr;
u32_t pupdr;
u32_t idr;
u32_t odr;
u32_t bsrr;
u32_t lckr;
u32_t afr[2];
#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32F3X) || \
defined(CONFIG_SOC_SERIES_STM32F7X) || \
defined(CONFIG_SOC_SERIES_STM32L0X) || \
defined(CONFIG_SOC_SERIES_STM32L4X)
u32_t brr;
#endif
#ifdef CONFIG_SOC_SERIES_STM32L4X
u32_t ascr;
#endif
#endif /* CONFIG_SOC_SERIES_STM32F1X */
};
/** /**
* @brief helper for configuration of GPIO pin * @brief helper for configuration of GPIO pin
* *

18
soc/arm/st_stm32/common/soc_syscfg_common.h
View file

@ -1,18 +0,0 @@
/*
* Copyright (c) 2018 Song Qiang <songqiang1304521@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SOC_SYSCFG_COMMON_H
#define __SOC_SYSCFG_COMMON_H
union syscfg_exticr {
u32_t val;
struct {
u16_t exti;
u16_t rsvd__16_31;
} bit;
};
#endif /* __STM32_SYSCFG_COMMON_H */

4
soc/arm/st_stm32/stm32f0/soc.h
View file

@ -55,6 +55,10 @@
#include <stm32f0xx_ll_spi.h> #include <stm32f0xx_ll_spi.h>
#endif #endif
#ifdef CONFIG_GPIO_STM32
#include <stm32f0xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */ #endif /* !_ASMLANGUAGE */
#endif /* _STM32F0_SOC_H_ */ #endif /* _STM32F0_SOC_H_ */

1
soc/arm/st_stm32/stm32f0/soc_registers.h
View file

@ -9,6 +9,5 @@
/* include register mapping headers */ /* include register mapping headers */
#include "flash_registers.h" #include "flash_registers.h"
#include "syscfg_registers.h"
#endif /* _STM32F0X_SOC_REGISTERS_H_ */ #endif /* _STM32F0X_SOC_REGISTERS_H_ */

57
soc/arm/st_stm32/stm32f0/syscfg_registers.h
View file

@ -1,57 +0,0 @@
/*
* Copyright (c) 2017 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* STM32F030x4/x6/x8/xC,
* STM32F070x6/xB advanced ARM ® -based MCUs
*
* Chapter 9: System configuration controller (SYSCFG)
*/
#include "../common/soc_syscfg_common.h"
union syscfg_cfgr1 {
u32_t val;
struct {
u32_t mem_mode :2 __packed;
u32_t rsvd__2_7 :6 __packed;
u32_t adc_dma_rmp :1 __packed;
u32_t usart1_tx_dma_rmp :1 __packed;
u32_t usart1_rx_dma_rmp :1 __packed;
u32_t tim16_dma_rmp :1 __packed;
u32_t tim17_dma_rmp :1 __packed;
u32_t rsvd__13_15 :3 __packed;
u32_t i2c_pb6_fmp :1 __packed;
u32_t i2c_pb7_fmp :1 __packed;
u32_t i2c_pb8_fmp :1 __packed;
u32_t i2c_pb9_fmp :1 __packed;
u32_t i2c1_fmp :1 __packed;
u32_t rsvd__21 :1 __packed;
u32_t i2c_pa9_fmp :1 __packed;
u32_t i2c_pa10_fmp :1 __packed;
u32_t rsvd__24_25 :2 __packed;
u32_t usart3_dma_rmp :1 __packed;
u32_t rsvd__27_31 :5 __packed;
} bit;
};
struct stm32_syscfg {
union syscfg_cfgr1 cfgr1;
u32_t rsvd;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t cfgr2;
};
#endif /* _STM32_SYSCFG_REGISTERS_H_ */

87
soc/arm/st_stm32/stm32f1/afio_registers.h
View file

@ -1,87 +0,0 @@
/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_AFIO_REGISTERS_H_
#define _STM32_AFIO_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
* advanced ARM(r)-based 32-bit MCUs
*
* Chapter 9: General-purpose and alternate-function I/Os
* (GPIOs and AFIOs)
*/
#include "../common/soc_syscfg_common.h"
/* 9.4.1 AFIO_EVCR */
union __afio_evcr {
u32_t val;
struct {
u32_t pin :4 __packed;
u32_t port :3 __packed;
u32_t evoe :1 __packed;
u32_t rsvd__8_31 :24 __packed;
} bit;
};
/* 9.4.2 AFIO_MAPR */
/* TODO: support connectivity line devices */
union __afio_mapr {
u32_t val;
struct {
u32_t spi1_remap :1 __packed;
u32_t i2c1_remap :1 __packed;
u32_t usart1_remap :1 __packed;
u32_t usart2_remap :1 __packed;
u32_t usart3_remap :2 __packed;
u32_t tim1_remap :2 __packed;
u32_t tim2_remap :2 __packed;
u32_t tim3_remap :2 __packed;
u32_t tim4_remap :1 __packed;
u32_t can_remap :2 __packed;
u32_t pd01_remap :1 __packed;
u32_t tim5ch4_iremap :1 __packed;
u32_t adc1_etrginj_remap :1 __packed;
u32_t adc1_etrgreg_remap :1 __packed;
u32_t adc2_etrginj_remap :1 __packed;
u32_t adc2_etrgreg_remap :1 __packed;
u32_t rsvd__21_23 :3 __packed;
u32_t swj_cfg :3 __packed;
u32_t rsvd__27_31 :5 __packed;
} bit;
};
/* 9.4.7 AFIO_MAPR2 */
union __afio_mapr2 {
u32_t val;
struct {
u32_t rsvd__0_4 :5 __packed;
u32_t tim9_remap :1 __packed;
u32_t tim10_remap :1 __packed;
u32_t tim11_remap :1 __packed;
u32_t tim13_remap :1 __packed;
u32_t tim14_remap :1 __packed;
u32_t fsmc_nadv :1 __packed;
u32_t rsvd__11_31 :21 __packed;
} bit;
};
/* 9.4 AFIO registers */
struct stm32_afio {
union __afio_evcr evcr;
union __afio_mapr mapr;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
union __afio_mapr2 mapr2;
};
#endif /* _STM32_AFIO_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32f1/soc.h
View file

@ -55,6 +55,10 @@
#include <stm32f1xx_ll_iwdg.h> #include <stm32f1xx_ll_iwdg.h>
#endif #endif
#ifdef CONFIG_GPIO_STM32
#include <stm32f1xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */ #endif /* !_ASMLANGUAGE */
#endif /* _STM32F1_SOC_H_ */ #endif /* _STM32F1_SOC_H_ */

1
soc/arm/st_stm32/stm32f1/soc_registers.h
View file

@ -8,7 +8,6 @@
#define _STM32F10X_SOC_REGISTERS_H_ #define _STM32F10X_SOC_REGISTERS_H_
/* include register mapping headers */ /* include register mapping headers */
#include "afio_registers.h"
#include "flash_registers.h" #include "flash_registers.h"
#endif /* _STM32F10X_SOC_REGISTERS_H_ */ #endif /* _STM32F10X_SOC_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32f2/soc.h
View file

@ -42,6 +42,10 @@
#include <stm32f2xx_ll_usart.h> #include <stm32f2xx_ll_usart.h>
#endif #endif
#ifdef CONFIG_GPIO_STM32
#include <stm32f2xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */ #endif /* !_ASMLANGUAGE */
#endif /* _STM32F2_SOC_H_ */ #endif /* _STM32F2_SOC_H_ */

1
soc/arm/st_stm32/stm32f2/soc_registers.h
View file

@ -8,6 +8,5 @@
#define _STM32F2X_SOC_REGISTERS_H_ #define _STM32F2X_SOC_REGISTERS_H_
/* include register mapping headers */ /* include register mapping headers */
#include "syscfg_registers.h"
#endif /* _STM32F2X_SOC_REGISTERS_H_ */ #endif /* _STM32F2X_SOC_REGISTERS_H_ */

32
soc/arm/st_stm32/stm32f2/syscfg_registers.h
View file

@ -1,32 +0,0 @@
/*
* Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* stm32f2X advanced ARM ® -based 32-bit MCUs
*
* Chapter 7: System configuration controller (SYSCFG)
*/
#include "../common/soc_syscfg_common.h"
/* 7.2 SYSCFG registers */
struct stm32_syscfg {
u32_t memrmp;
u32_t pmc;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t cmpcr;
};
#endif /* _STM32_SYSCFG_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32f3/soc.h
View file

@ -62,6 +62,10 @@
#include <stm32f3xx_ll_pwr.h> #include <stm32f3xx_ll_pwr.h>
#endif #endif
#ifdef CONFIG_GPIO_STM32
#include <stm32f3xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */ #endif /* !_ASMLANGUAGE */
#endif /* _STM32F3_SOC_H_ */ #endif /* _STM32F3_SOC_H_ */

1
soc/arm/st_stm32/stm32f3/soc_registers.h
View file

@ -9,6 +9,5 @@
/* include register mapping headers */ /* include register mapping headers */
#include "flash_registers.h" #include "flash_registers.h"
#include "syscfg_registers.h"
#endif /* _STM32F3X_SOC_REGISTERS_H_ */ #endif /* _STM32F3X_SOC_REGISTERS_H_ */

80
soc/arm/st_stm32/stm32f3/syscfg_registers.h
View file

@ -1,80 +0,0 @@
/*
* Copyright (c) 2016 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* STM32F303xB/C/D/E, STM32F303x6/8, STM32F328x8, STM32F358xC,
* STM32F398xE advanced ARM(r)-based MCUs
*/
#include "../common/soc_syscfg_common.h"
union syscfg_cfgr1 {
u32_t val;
struct {
u32_t mem_mode :2 __packed;
u32_t rsvd__2_5 :4 __packed;
u32_t tim1_itr3_rmo :1 __packed;
u32_t dac_trig_rmp :1 __packed;
u32_t rsvd__8_10 :3 __packed;
u32_t tim16_dma_rmp :1 __packed;
u32_t tim17_dma_rmp :1 __packed;
u32_t tim16_dac1_dma_rmp :1 __packed;
u32_t tim17_dac2_dma_rmp :1 __packed;
u32_t dac2_ch1_dma_rmp :1 __packed;
u32_t i2c_pb6_fmp :1 __packed;
u32_t i2c_pb7_fmp :1 __packed;
u32_t i2c_pb8_fmp :1 __packed;
u32_t i2c_pb9_fmp :1 __packed;
u32_t i2c1_fmp :1 __packed;
u32_t rsvd__21 :1 __packed;
u32_t encoder_mode :2 __packed;
u32_t rsvd__24_25 :2 __packed;
u32_t fpu_ie :6 __packed;
} bit;
};
union syscfg_rcr {
u32_t val;
struct {
u32_t page0_wp :1 __packed;
u32_t page1_wp :1 __packed;
u32_t page2_wp :1 __packed;
u32_t page3_wp :1 __packed;
u32_t rsvd__4_31 :28 __packed;
} bit;
};
struct stm32_syscfg {
union syscfg_cfgr1 cfgr1;
union syscfg_rcr rcr;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t cfgr2;
u32_t rsvd_0x1C;
u32_t rsvd_0x20;
u32_t rsvd_0x24;
u32_t rsvd_0x28;
u32_t rsvd_0x2C;
u32_t rsvd_0x30;
u32_t rsvd_0x34;
u32_t rsvd_0x38;
u32_t rsvd_0x3C;
u32_t rsvd_0x40;
u32_t rsvd_0x44;
u32_t rsvd_0x48;
u32_t rsvd_0x4C;
u32_t cfgr3;
};
#endif /* _STM32_GPIO_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32f4/soc.h
View file

@ -65,6 +65,10 @@
#include <stm32f4xx_ll_pwr.h> #include <stm32f4xx_ll_pwr.h>
#endif #endif
#ifdef CONFIG_GPIO_STM32
#include <stm32f4xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */ #endif /* !_ASMLANGUAGE */
#endif /* _STM32F4_SOC_H_ */ #endif /* _STM32F4_SOC_H_ */

1
soc/arm/st_stm32/stm32f4/soc_registers.h
View file

@ -9,6 +9,5 @@
/* include register mapping headers */ /* include register mapping headers */
#include "flash_registers.h" #include "flash_registers.h"
#include "syscfg_registers.h"
#endif /* _STM32F4_SOC_REGISTERS_H_ */ #endif /* _STM32F4_SOC_REGISTERS_H_ */

31
soc/arm/st_stm32/stm32f4/syscfg_registers.h
View file

@ -1,31 +0,0 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
/**
* @brief Driver for GPIO of STM32F4X family processor.
*
* Based on reference manual:
* RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
* advanced ARM(r)-based 32-bit MCUs
*/
#include "../common/soc_syscfg_common.h"
/* 7.2 SYSCFG registers */
struct stm32_syscfg {
u32_t memrmp;
u32_t pmc;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t cmpcr;
};
#endif /* _STM32_SYSCFG_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32f7/soc.h
View file

@ -60,6 +60,10 @@
#include <stm32f7xx_ll_pwr.h> #include <stm32f7xx_ll_pwr.h>
#endif #endif
#ifdef CONFIG_GPIO_STM32
#include <stm32f7xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */ #endif /* !_ASMLANGUAGE */
#endif /* _STM32F7_SOC_H_ */ #endif /* _STM32F7_SOC_H_ */

1
soc/arm/st_stm32/stm32f7/soc_registers.h
View file

@ -9,6 +9,5 @@
/* include register mapping headers */ /* include register mapping headers */
#include "flash_registers.h" #include "flash_registers.h"
#include "syscfg_registers.h"
#endif /* _STM32F7_SOC_REGISTERS_H_ */ #endif /* _STM32F7_SOC_REGISTERS_H_ */

31
soc/arm/st_stm32/stm32f7/syscfg_registers.h
View file

@ -1,31 +0,0 @@
/*
* Copyright (c) 2018 Yurii Hamann
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
/**
* @brief Driver for GPIO of STM32F7X family processor.
*
* Based on reference manual:
* RM0385 Reference manual STM32F75xxx and STM32F74xxx
* advanced ARM(r)-based 32-bit MCUs
*/
#include "../common/soc_syscfg_common.h"
/* 7.2 SYSCFG registers */
struct stm32_syscfg {
u32_t memrmp;
u32_t pmc;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t cmpcr;
};
#endif /* _STM32_SYSCFG_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32l0/soc.h
View file

@ -52,6 +52,10 @@
#include <stm32l0xx_ll_spi.h> #include <stm32l0xx_ll_spi.h>
#endif #endif
#ifdef CONFIG_GPIO_STM32
#include <stm32l0xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */ #endif /* !_ASMLANGUAGE */
#endif /* _STM32L0_SOC_H_ */ #endif /* _STM32L0_SOC_H_ */

1
soc/arm/st_stm32/stm32l0/soc_registers.h
View file

@ -8,7 +8,6 @@
#define _STM32L0X_SOC_REGISTERS_H_ #define _STM32L0X_SOC_REGISTERS_H_
/* include register mapping headers */ /* include register mapping headers */
#include "syscfg_registers.h"
#endif /* _STM32L0X_SOC_REGISTERS_H_ */ #endif /* _STM32L0X_SOC_REGISTERS_H_ */

33
soc/arm/st_stm32/stm32l0/syscfg_registers.h
View file

@ -1,33 +0,0 @@
/*
* Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* STM32L0X advanced ARM ® -based 32-bit MCUs
*
* Chapter 10: System configuration controller (SYSCFG)
*/
#include "../common/soc_syscfg_common.h"
struct stm32_syscfg {
u32_t cfgr1;
u32_t cfgr2;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t comp1_ctrl;
u32_t comp2_ctrl;
u32_t cfgr3;
};
#endif /* _STM32_SYSCFG_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32l4/soc.h
View file

@ -79,6 +79,10 @@
#include <stm32l4xx_ll_pwr.h> #include <stm32l4xx_ll_pwr.h>
#endif /* CONFIG_USB */ #endif /* CONFIG_USB */
#ifdef CONFIG_GPIO_STM32
#include <stm32l4xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */ #endif /* !_ASMLANGUAGE */
#endif /* _STM32L4X_SOC_H_ */ #endif /* _STM32L4X_SOC_H_ */

1
soc/arm/st_stm32/stm32l4/soc_registers.h
View file

@ -10,6 +10,5 @@
/* include register mapping headers */ /* include register mapping headers */
#include "flash_registers.h" #include "flash_registers.h"
#include "syscfg_registers.h"
#endif /* _STM32L4X_SOC_REGISTERS_H_ */ #endif /* _STM32L4X_SOC_REGISTERS_H_ */

26
soc/arm/st_stm32/stm32l4/syscfg_registers.h
View file

@ -1,26 +0,0 @@
/*
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
#include "../common/soc_syscfg_common.h"
/* SYSCFG registers */
struct stm32_syscfg {
u32_t memrmp;
u32_t cfgr1;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t scsr;
u32_t cfgr2;
u32_t swpr;
u32_t skr;
};
#endif /* _STM32_SYSCFG_REGISTERS_H_ */