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soc: arm: st_stm32: Using LL library to implement gpio functions

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The original implementation of gpio functions access registers
directly. Using LL library can add a set of unifying access
functions for all series of stm32 for avoiding accessing low level
code, and improve readability.

Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
This commit is contained in:
Song Qiang 2019-01-08 18:12:04 +08:00 • committed by Kumar Gala
commit 2fb616efbe
27 changed files with 174 additions and 565 deletions
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18
soc/arm/st_stm32/common/soc_syscfg_common.h
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@ -1,18 +0,0 @@
/*
* Copyright (c) 2018 Song Qiang <songqiang1304521@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SOC_SYSCFG_COMMON_H
#define __SOC_SYSCFG_COMMON_H
union syscfg_exticr {
u32_t val;
struct {
u16_t exti;
u16_t rsvd__16_31;
} bit;
};
#endif /* __STM32_SYSCFG_COMMON_H */

4
soc/arm/st_stm32/stm32f0/soc.h
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@ -55,6 +55,10 @@
#include <stm32f0xx_ll_spi.h>
#endif
#ifdef CONFIG_GPIO_STM32
#include <stm32f0xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */
#endif /* _STM32F0_SOC_H_ */

1
soc/arm/st_stm32/stm32f0/soc_registers.h
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@ -9,6 +9,5 @@
/* include register mapping headers */
#include "flash_registers.h"
#include "syscfg_registers.h"
#endif /* _STM32F0X_SOC_REGISTERS_H_ */

57
soc/arm/st_stm32/stm32f0/syscfg_registers.h
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@ -1,57 +0,0 @@
/*
* Copyright (c) 2017 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* STM32F030x4/x6/x8/xC,
* STM32F070x6/xB advanced ARM ® -based MCUs
*
* Chapter 9: System configuration controller (SYSCFG)
*/
#include "../common/soc_syscfg_common.h"
union syscfg_cfgr1 {
u32_t val;
struct {
u32_t mem_mode :2 __packed;
u32_t rsvd__2_7 :6 __packed;
u32_t adc_dma_rmp :1 __packed;
u32_t usart1_tx_dma_rmp :1 __packed;
u32_t usart1_rx_dma_rmp :1 __packed;
u32_t tim16_dma_rmp :1 __packed;
u32_t tim17_dma_rmp :1 __packed;
u32_t rsvd__13_15 :3 __packed;
u32_t i2c_pb6_fmp :1 __packed;
u32_t i2c_pb7_fmp :1 __packed;
u32_t i2c_pb8_fmp :1 __packed;
u32_t i2c_pb9_fmp :1 __packed;
u32_t i2c1_fmp :1 __packed;
u32_t rsvd__21 :1 __packed;
u32_t i2c_pa9_fmp :1 __packed;
u32_t i2c_pa10_fmp :1 __packed;
u32_t rsvd__24_25 :2 __packed;
u32_t usart3_dma_rmp :1 __packed;
u32_t rsvd__27_31 :5 __packed;
} bit;
};
struct stm32_syscfg {
union syscfg_cfgr1 cfgr1;
u32_t rsvd;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t cfgr2;
};
#endif /* _STM32_SYSCFG_REGISTERS_H_ */

87
soc/arm/st_stm32/stm32f1/afio_registers.h
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@ -1,87 +0,0 @@
/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_AFIO_REGISTERS_H_
#define _STM32_AFIO_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
* advanced ARM(r)-based 32-bit MCUs
*
* Chapter 9: General-purpose and alternate-function I/Os
* (GPIOs and AFIOs)
*/
#include "../common/soc_syscfg_common.h"
/* 9.4.1 AFIO_EVCR */
union __afio_evcr {
u32_t val;
struct {
u32_t pin :4 __packed;
u32_t port :3 __packed;
u32_t evoe :1 __packed;
u32_t rsvd__8_31 :24 __packed;
} bit;
};
/* 9.4.2 AFIO_MAPR */
/* TODO: support connectivity line devices */
union __afio_mapr {
u32_t val;
struct {
u32_t spi1_remap :1 __packed;
u32_t i2c1_remap :1 __packed;
u32_t usart1_remap :1 __packed;
u32_t usart2_remap :1 __packed;
u32_t usart3_remap :2 __packed;
u32_t tim1_remap :2 __packed;
u32_t tim2_remap :2 __packed;
u32_t tim3_remap :2 __packed;
u32_t tim4_remap :1 __packed;
u32_t can_remap :2 __packed;
u32_t pd01_remap :1 __packed;
u32_t tim5ch4_iremap :1 __packed;
u32_t adc1_etrginj_remap :1 __packed;
u32_t adc1_etrgreg_remap :1 __packed;
u32_t adc2_etrginj_remap :1 __packed;
u32_t adc2_etrgreg_remap :1 __packed;
u32_t rsvd__21_23 :3 __packed;
u32_t swj_cfg :3 __packed;
u32_t rsvd__27_31 :5 __packed;
} bit;
};
/* 9.4.7 AFIO_MAPR2 */
union __afio_mapr2 {
u32_t val;
struct {
u32_t rsvd__0_4 :5 __packed;
u32_t tim9_remap :1 __packed;
u32_t tim10_remap :1 __packed;
u32_t tim11_remap :1 __packed;
u32_t tim13_remap :1 __packed;
u32_t tim14_remap :1 __packed;
u32_t fsmc_nadv :1 __packed;
u32_t rsvd__11_31 :21 __packed;
} bit;
};
/* 9.4 AFIO registers */
struct stm32_afio {
union __afio_evcr evcr;
union __afio_mapr mapr;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
union __afio_mapr2 mapr2;
};
#endif /* _STM32_AFIO_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32f1/soc.h
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@ -55,6 +55,10 @@
#include <stm32f1xx_ll_iwdg.h>
#endif
#ifdef CONFIG_GPIO_STM32
#include <stm32f1xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */
#endif /* _STM32F1_SOC_H_ */

1
soc/arm/st_stm32/stm32f1/soc_registers.h
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@ -8,7 +8,6 @@
#define _STM32F10X_SOC_REGISTERS_H_
/* include register mapping headers */
#include "afio_registers.h"
#include "flash_registers.h"
#endif /* _STM32F10X_SOC_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32f2/soc.h
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@ -42,6 +42,10 @@
#include <stm32f2xx_ll_usart.h>
#endif
#ifdef CONFIG_GPIO_STM32
#include <stm32f2xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */
#endif /* _STM32F2_SOC_H_ */

1
soc/arm/st_stm32/stm32f2/soc_registers.h
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@ -8,6 +8,5 @@
#define _STM32F2X_SOC_REGISTERS_H_
/* include register mapping headers */
#include "syscfg_registers.h"
#endif /* _STM32F2X_SOC_REGISTERS_H_ */

32
soc/arm/st_stm32/stm32f2/syscfg_registers.h
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@ -1,32 +0,0 @@
/*
* Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* stm32f2X advanced ARM ® -based 32-bit MCUs
*
* Chapter 7: System configuration controller (SYSCFG)
*/
#include "../common/soc_syscfg_common.h"
/* 7.2 SYSCFG registers */
struct stm32_syscfg {
u32_t memrmp;
u32_t pmc;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t cmpcr;
};
#endif /* _STM32_SYSCFG_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32f3/soc.h
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@ -62,6 +62,10 @@
#include <stm32f3xx_ll_pwr.h>
#endif
#ifdef CONFIG_GPIO_STM32
#include <stm32f3xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */
#endif /* _STM32F3_SOC_H_ */

1
soc/arm/st_stm32/stm32f3/soc_registers.h
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@ -9,6 +9,5 @@
/* include register mapping headers */
#include "flash_registers.h"
#include "syscfg_registers.h"
#endif /* _STM32F3X_SOC_REGISTERS_H_ */

80
soc/arm/st_stm32/stm32f3/syscfg_registers.h
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@ -1,80 +0,0 @@
/*
* Copyright (c) 2016 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* STM32F303xB/C/D/E, STM32F303x6/8, STM32F328x8, STM32F358xC,
* STM32F398xE advanced ARM(r)-based MCUs
*/
#include "../common/soc_syscfg_common.h"
union syscfg_cfgr1 {
u32_t val;
struct {
u32_t mem_mode :2 __packed;
u32_t rsvd__2_5 :4 __packed;
u32_t tim1_itr3_rmo :1 __packed;
u32_t dac_trig_rmp :1 __packed;
u32_t rsvd__8_10 :3 __packed;
u32_t tim16_dma_rmp :1 __packed;
u32_t tim17_dma_rmp :1 __packed;
u32_t tim16_dac1_dma_rmp :1 __packed;
u32_t tim17_dac2_dma_rmp :1 __packed;
u32_t dac2_ch1_dma_rmp :1 __packed;
u32_t i2c_pb6_fmp :1 __packed;
u32_t i2c_pb7_fmp :1 __packed;
u32_t i2c_pb8_fmp :1 __packed;
u32_t i2c_pb9_fmp :1 __packed;
u32_t i2c1_fmp :1 __packed;
u32_t rsvd__21 :1 __packed;
u32_t encoder_mode :2 __packed;
u32_t rsvd__24_25 :2 __packed;
u32_t fpu_ie :6 __packed;
} bit;
};
union syscfg_rcr {
u32_t val;
struct {
u32_t page0_wp :1 __packed;
u32_t page1_wp :1 __packed;
u32_t page2_wp :1 __packed;
u32_t page3_wp :1 __packed;
u32_t rsvd__4_31 :28 __packed;
} bit;
};
struct stm32_syscfg {
union syscfg_cfgr1 cfgr1;
union syscfg_rcr rcr;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t cfgr2;
u32_t rsvd_0x1C;
u32_t rsvd_0x20;
u32_t rsvd_0x24;
u32_t rsvd_0x28;
u32_t rsvd_0x2C;
u32_t rsvd_0x30;
u32_t rsvd_0x34;
u32_t rsvd_0x38;
u32_t rsvd_0x3C;
u32_t rsvd_0x40;
u32_t rsvd_0x44;
u32_t rsvd_0x48;
u32_t rsvd_0x4C;
u32_t cfgr3;
};
#endif /* _STM32_GPIO_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32f4/soc.h
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@ -65,6 +65,10 @@
#include <stm32f4xx_ll_pwr.h>
#endif
#ifdef CONFIG_GPIO_STM32
#include <stm32f4xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */
#endif /* _STM32F4_SOC_H_ */

1
soc/arm/st_stm32/stm32f4/soc_registers.h
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@ -9,6 +9,5 @@
/* include register mapping headers */
#include "flash_registers.h"
#include "syscfg_registers.h"
#endif /* _STM32F4_SOC_REGISTERS_H_ */

31
soc/arm/st_stm32/stm32f4/syscfg_registers.h
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@ -1,31 +0,0 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
/**
* @brief Driver for GPIO of STM32F4X family processor.
*
* Based on reference manual:
* RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
* advanced ARM(r)-based 32-bit MCUs
*/
#include "../common/soc_syscfg_common.h"
/* 7.2 SYSCFG registers */
struct stm32_syscfg {
u32_t memrmp;
u32_t pmc;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t cmpcr;
};
#endif /* _STM32_SYSCFG_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32f7/soc.h
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@ -60,6 +60,10 @@
#include <stm32f7xx_ll_pwr.h>
#endif
#ifdef CONFIG_GPIO_STM32
#include <stm32f7xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */
#endif /* _STM32F7_SOC_H_ */

1
soc/arm/st_stm32/stm32f7/soc_registers.h
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@ -9,6 +9,5 @@
/* include register mapping headers */
#include "flash_registers.h"
#include "syscfg_registers.h"
#endif /* _STM32F7_SOC_REGISTERS_H_ */

31
soc/arm/st_stm32/stm32f7/syscfg_registers.h
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@ -1,31 +0,0 @@
/*
* Copyright (c) 2018 Yurii Hamann
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
/**
* @brief Driver for GPIO of STM32F7X family processor.
*
* Based on reference manual:
* RM0385 Reference manual STM32F75xxx and STM32F74xxx
* advanced ARM(r)-based 32-bit MCUs
*/
#include "../common/soc_syscfg_common.h"
/* 7.2 SYSCFG registers */
struct stm32_syscfg {
u32_t memrmp;
u32_t pmc;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t cmpcr;
};
#endif /* _STM32_SYSCFG_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32l0/soc.h
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@ -52,6 +52,10 @@
#include <stm32l0xx_ll_spi.h>
#endif
#ifdef CONFIG_GPIO_STM32
#include <stm32l0xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */
#endif /* _STM32L0_SOC_H_ */

1
soc/arm/st_stm32/stm32l0/soc_registers.h
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@ -8,7 +8,6 @@
#define _STM32L0X_SOC_REGISTERS_H_
/* include register mapping headers */
#include "syscfg_registers.h"
#endif /* _STM32L0X_SOC_REGISTERS_H_ */

33
soc/arm/st_stm32/stm32l0/syscfg_registers.h
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@ -1,33 +0,0 @@
/*
* Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
/**
* @brief
*
* Based on reference manual:
* STM32L0X advanced ARM ® -based 32-bit MCUs
*
* Chapter 10: System configuration controller (SYSCFG)
*/
#include "../common/soc_syscfg_common.h"
struct stm32_syscfg {
u32_t cfgr1;
u32_t cfgr2;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t comp1_ctrl;
u32_t comp2_ctrl;
u32_t cfgr3;
};
#endif /* _STM32_SYSCFG_REGISTERS_H_ */

4
soc/arm/st_stm32/stm32l4/soc.h
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@ -79,6 +79,10 @@
#include <stm32l4xx_ll_pwr.h>
#endif /* CONFIG_USB */
#ifdef CONFIG_GPIO_STM32
#include <stm32l4xx_ll_gpio.h>
#endif
#endif /* !_ASMLANGUAGE */
#endif /* _STM32L4X_SOC_H_ */

1
soc/arm/st_stm32/stm32l4/soc_registers.h
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@ -10,6 +10,5 @@
/* include register mapping headers */
#include "flash_registers.h"
#include "syscfg_registers.h"
#endif /* _STM32L4X_SOC_REGISTERS_H_ */

26
soc/arm/st_stm32/stm32l4/syscfg_registers.h
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@ -1,26 +0,0 @@
/*
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32_SYSCFG_REGISTERS_H_
#define _STM32_SYSCFG_REGISTERS_H_
#include "../common/soc_syscfg_common.h"
/* SYSCFG registers */
struct stm32_syscfg {
u32_t memrmp;
u32_t cfgr1;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
u32_t scsr;
u32_t cfgr2;
u32_t swpr;
u32_t skr;
};
#endif /* _STM32_SYSCFG_REGISTERS_H_ */