diff --git a/boards/xtensa/intel_adsp_cavs15/tools/adsplog.py b/boards/xtensa/intel_adsp_cavs15/tools/adsplog.py
index 208a8f374b5..f7d27a6c00a 100755
--- a/boards/xtensa/intel_adsp_cavs15/tools/adsplog.py
+++ b/boards/xtensa/intel_adsp_cavs15/tools/adsplog.py
@@ -28,7 +28,7 @@ import mmap
 # data, followed a 16 bit "ID" number, followed by a null-terminated
 # string in the final 60 bytes (or 60 non-null bytes of log data).
 # The DSP firmware will write sequential IDs into the buffer starting
-# from an ID of zero in the first slot, and wrapping at the end.
+# from an ID of '1' in the 0th slot, and wrapping at the end.
 
 MAP_SIZE = 8192
 SLOT_SIZE = 64
diff --git a/boards/xtensa/intel_adsp_cavs15/tools/lib/loglist.py b/boards/xtensa/intel_adsp_cavs15/tools/lib/loglist.py
index 53399eb2ee9..9e73d23c500 100644
--- a/boards/xtensa/intel_adsp_cavs15/tools/lib/loglist.py
+++ b/boards/xtensa/intel_adsp_cavs15/tools/lib/loglist.py
@@ -35,6 +35,8 @@ class Loglist:
         magic = read_bytes(slot[0:2])
 
         if magic == MAGIC:
+            # Sequence number starting from 1, see
+            # soc/xtensa/intel_adsp/common/trace_out.c
             id_num = read_bytes(slot[2:4])
             before_first_zero = slot[4:].split(b'\x00')[0]
             logstr = before_first_zero.decode(errors='replace')
diff --git a/soc/xtensa/intel_adsp/common/trace_out.c b/soc/xtensa/intel_adsp/common/trace_out.c
index 9df11067c09..98e0a475c57 100644
--- a/soc/xtensa/intel_adsp/common/trace_out.c
+++ b/soc/xtensa/intel_adsp/common/trace_out.c
@@ -11,8 +11,8 @@
  * for communication with the host processor as a shared memory
  * region.  The protocol uses an array of 64-byte "slots", each of
  * which is prefixed by a 16 bit magic number followed by a sequential
- * ID number.  The remaining bytes are a (potentially nul-terminated)
- * string containing output data.
+ * ID number starting from 1.  The remaining bytes are a (potentially
+ * nul-terminated) string containing output data.
  *
  * IMPORTANT NOTE on cache coherence: the shared memory window is in
  * HP-SRAM.  Each DSP core has an L1 cache that is incoherent (!) from