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intel_adsp: ace15: shim: update wovrco request bit

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Updating value of WOVRCO request bit in CLKCTL register according to the
documentation. Previus value was mask used for clock enabling.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit is contained in:
Tomasz Leman 2023-09-07 13:27:46 +02:00 • committed by Fabio Baltieri
commit 2f2689e3d3
1 changed files with 1 additions and 1 deletions
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soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_shim.h
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@ -140,7 +140,7 @@ struct ace_dfpmccu {
#endif /* _ASMLANGUAGE */ #endif /* _ASMLANGUAGE */
#define ACE_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */ #define ACE_CLKCTL_WOVCRO BIT(21) /* Request WOVCRO clock */
#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) #define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0) #define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)