diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index bf2312736db..e4a9609936c 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -35,6 +35,9 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SMARTBOND clock_cont zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NUMAKER_SCC clock_control_numaker_scc.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_S32 clock_control_nxp_s32.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC clock_control_renesas_ra_cgc.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_ROOT clock_control_renesas_rx_root_cgc.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_PLL clock_control_renesas_rx_pll_cgc.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_PCLK clock_control_renesas_rx_pclk_cgc.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RZ_CPG clock_control_renesas_rz_cpg.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ clock_control_ambiq.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM clock_control_pwm.c) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index 229a45792e8..16db5c77a15 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -88,6 +88,8 @@ source "drivers/clock_control/Kconfig.agilex5" source "drivers/clock_control/Kconfig.renesas_ra_cgc" +source "drivers/clock_control/Kconfig.renesas_rx_cgc" + source "drivers/clock_control/Kconfig.renesas_rz_cpg" source "drivers/clock_control/Kconfig.max32" diff --git a/drivers/clock_control/Kconfig.renesas_rx_cgc b/drivers/clock_control/Kconfig.renesas_rx_cgc new file mode 100644 index 00000000000..21ea76e55f2 --- /dev/null +++ b/drivers/clock_control/Kconfig.renesas_rx_cgc @@ -0,0 +1,31 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config CLOCK_CONTROL_RENESAS_RX_CGC + bool "RX CGC driver" + default y + depends on SOC_FAMILY_RENESAS_RX + help + Enable support for Renesas RX CGC driver. + +if CLOCK_CONTROL_RENESAS_RX_CGC + +config CLOCK_CONTROL_RENESAS_RX_ROOT + bool "Renesas RX root clock source" + default y + help + Enable Renesas RX root clock + +config CLOCK_CONTROL_RENESAS_RX_PLL + bool "Renesas RX root clock source" + default y + help + Enable Renesas RX PLL + +config CLOCK_CONTROL_RENESAS_RX_PCLK + bool "Renesas RX root clock source" + default y + help + Enable Renesas RX PCLK + +endif diff --git a/drivers/clock_control/clock_control_renesas_rx_pclk_cgc.c b/drivers/clock_control/clock_control_renesas_rx_pclk_cgc.c new file mode 100644 index 00000000000..c518fb35a5b --- /dev/null +++ b/drivers/clock_control/clock_control_renesas_rx_pclk_cgc.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define DT_DRV_COMPAT renesas_rx_cgc_pclk + +#include +#include +#include +#include +#include +#include + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pclkblock), okay) +#define MSTP_REGS_ELEM(node_id, prop, idx) \ + [DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)] = \ + (volatile uint32_t *)DT_REG_ADDR_BY_IDX(node_id, idx), + +static volatile uint32_t *mstp_regs[] = { + DT_FOREACH_PROP_ELEM(DT_NODELABEL(pclkblock), reg_names, MSTP_REGS_ELEM)}; +#else +static volatile uint32_t *mstp_regs[] = {}; +#endif + +static int clock_control_renesas_rx_on(const struct device *dev, clock_control_subsys_t sys) +{ + struct clock_control_rx_subsys_cfg *subsys_clk = (struct clock_control_rx_subsys_cfg *)sys; + + if (!dev || !sys) { + return -EINVAL; + } + + renesas_rx_register_protect_disable(RENESAS_RX_REG_PROTECT_LPC_CGC_SWR); + WRITE_BIT(*mstp_regs[subsys_clk->mstp], subsys_clk->stop_bit, false); + renesas_rx_register_protect_enable(RENESAS_RX_REG_PROTECT_LPC_CGC_SWR); + + return 0; +} + +static int clock_control_renesas_rx_off(const struct device *dev, clock_control_subsys_t sys) +{ + struct clock_control_rx_subsys_cfg *subsys_clk = (struct clock_control_rx_subsys_cfg *)sys; + + if (!dev || !sys) { + return -EINVAL; + } + + renesas_rx_register_protect_disable(RENESAS_RX_REG_PROTECT_LPC_CGC_SWR); + WRITE_BIT(*mstp_regs[subsys_clk->mstp], subsys_clk->stop_bit, true); + renesas_rx_register_protect_enable(RENESAS_RX_REG_PROTECT_LPC_CGC_SWR); + + return 0; +} + +static int clock_control_renesas_rx_get_rate(const struct device *dev, clock_control_subsys_t sys, + uint32_t *rate) +{ + const struct clock_control_rx_pclk_cfg *config = dev->config; + uint32_t clk_src_rate; + uint32_t clk_div_val; + int ret; + + if (!device_is_ready(dev)) { + return -ENODEV; + } + + ret = clock_control_get_rate(config->clock_src_dev, NULL, &clk_src_rate); + if (ret) { + return ret; + } + + clk_div_val = config->clk_div; + *rate = clk_src_rate / clk_div_val; + + return 0; +} + +static DEVICE_API(clock_control, clock_control_renesas_rx_api) = { + .on = clock_control_renesas_rx_on, + .off = clock_control_renesas_rx_off, + .get_rate = clock_control_renesas_rx_get_rate, +}; + +#define RENESAS_RX_CLOCK_SOURCE(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, clocks), (DEVICE_DT_GET(DT_CLOCKS_CTLR(node_id))), \ + DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(node_id)))) + +#define INIT_PCLK(node_id) \ + static const struct clock_control_rx_pclk_cfg clock_control_cfg_##node_id = { \ + .clock_src_dev = RENESAS_RX_CLOCK_SOURCE(node_id), \ + .clk_div = DT_INST_PROP_OR(node_id, div, 1), \ + }; \ + DEVICE_DT_INST_DEFINE(node_id, NULL, NULL, NULL, &clock_control_cfg_##node_id, \ + PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \ + &clock_control_renesas_rx_api); + +DT_INST_FOREACH_STATUS_OKAY(INIT_PCLK); diff --git a/drivers/clock_control/clock_control_renesas_rx_pll_cgc.c b/drivers/clock_control/clock_control_renesas_rx_pll_cgc.c new file mode 100644 index 00000000000..e085800bd44 --- /dev/null +++ b/drivers/clock_control/clock_control_renesas_rx_pll_cgc.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT renesas_rx_cgc_pll + +#include +#include +#include +#include +#include +#include + +static int clock_control_renesas_rx_pll_on(const struct device *dev, clock_control_subsys_t sys) +{ + return -ENOTSUP; +} + +static int clock_control_renesas_rx_pll_off(const struct device *dev, clock_control_subsys_t sys) +{ + return -ENOTSUP; +} + +static enum clock_control_status clock_control_renesas_rx_pll_get_status(const struct device *dev, + clock_control_subsys_t sys) +{ + return CLOCK_CONTROL_STATUS_ON; +} + +static int clock_control_renesas_rx_pll_get_rate(const struct device *dev, + clock_control_subsys_t sys, uint32_t *rate) +{ + const struct clock_control_rx_pll_cfg *config = dev->config; + struct clock_control_rx_pll_data *data = dev->data; + float pll_multiplier; + float pll_divider; + uint32_t pll_clock_freq; + uint32_t clock_dev_freq; + int ret; + + if (!device_is_ready(dev)) { + return -ENODEV; + } + + /* Get the clock frequency of PLL clock device */ + ret = clock_control_get_rate(config->clock_dev, NULL, &clock_dev_freq); + if (ret) { + return ret; + } + + /* Calculate the PLL multiple and divider */ + pll_multiplier = (data->pll_mul + 1) / (2.0); + pll_divider = data->pll_div; + + /* Calculate PLL clock frequency */ + pll_clock_freq = ((clock_dev_freq / pll_divider) * pll_multiplier); + + *rate = pll_clock_freq; + return 0; +} + +static DEVICE_API(clock_control, clock_control_renesas_rx_pll_api) = { + .on = clock_control_renesas_rx_pll_on, + .off = clock_control_renesas_rx_pll_off, + .get_status = clock_control_renesas_rx_pll_get_status, + .get_rate = clock_control_renesas_rx_pll_get_rate, +}; + +#define PLL_CLK_INIT(idx) \ + static struct clock_control_rx_pll_cfg pll_cfg##idx = { \ + .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_DRV_INST(idx))), \ + }; \ + static struct clock_control_rx_pll_data pll_data##idx = { \ + .pll_div = DT_INST_PROP(idx, div), \ + .pll_mul = DT_INST_PROP(idx, mul), \ + }; \ + DEVICE_DT_INST_DEFINE(idx, NULL, NULL, &pll_data##idx, &pll_cfg##idx, PRE_KERNEL_1, \ + CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \ + &clock_control_renesas_rx_pll_api); + +DT_INST_FOREACH_STATUS_OKAY(PLL_CLK_INIT); diff --git a/drivers/clock_control/clock_control_renesas_rx_root_cgc.c b/drivers/clock_control/clock_control_renesas_rx_root_cgc.c new file mode 100644 index 00000000000..25ed0da71d7 --- /dev/null +++ b/drivers/clock_control/clock_control_renesas_rx_root_cgc.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT renesas_rx_cgc_root_clock + +#include +#include +#include +#include +#include + +static int clock_control_renesas_rx_root_on(const struct device *dev, clock_control_subsys_t sys) +{ + return -ENOTSUP; +} + +static int clock_control_renesas_rx_root_off(const struct device *dev, clock_control_subsys_t sys) +{ + return -ENOTSUP; +} + +static int clock_control_renesas_rx_root_get_rate(const struct device *dev, + clock_control_subsys_t sys, uint32_t *rate) +{ + const struct clock_control_rx_root_cfg *config = dev->config; + + ARG_UNUSED(sys); + + if (!device_is_ready(dev)) { + return -ENODEV; + } + + *rate = config->rate; + return 0; +} + +static int clock_control_rx_init(const struct device *dev) +{ + ARG_UNUSED(dev); +#if CONFIG_HAS_RENESAS_RX_RDP + /* Call to HAL layer to initialize system clock and peripheral clock */ + mcu_clock_setup(); +#endif + return 0; +} + +static DEVICE_API(clock_control, clock_control_renesas_rx_root_api) = { + .on = clock_control_renesas_rx_root_on, + .off = clock_control_renesas_rx_root_off, + .get_rate = clock_control_renesas_rx_root_get_rate, +}; + +#define ROOT_CLK_INIT(idx) \ + static const struct clock_control_rx_root_cfg clock_control_rx_root_cfg##idx = { \ + .rate = DT_INST_PROP(idx, clock_frequency), \ + }; \ + DEVICE_DT_INST_DEFINE(idx, &clock_control_rx_init, NULL, NULL, \ + &clock_control_rx_root_cfg##idx, PRE_KERNEL_1, \ + CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \ + &clock_control_renesas_rx_root_api); + +DT_INST_FOREACH_STATUS_OKAY(ROOT_CLK_INIT); diff --git a/dts/bindings/clock/renesas,rx-cgc-pclk-block.yaml b/dts/bindings/clock/renesas,rx-cgc-pclk-block.yaml new file mode 100644 index 00000000000..d934bd3ffaa --- /dev/null +++ b/dts/bindings/clock/renesas,rx-cgc-pclk-block.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RX clock control node pclk block + +compatible: "renesas,rx-cgc-pclk-block" + +include: [clock-controller.yaml, base.yaml] + +properties: + clocks: + description: | + Select the clock source for pclk block. + If you want to use different clock source for child node, + select it there diff --git a/dts/bindings/clock/renesas,rx-cgc-pclk.yaml b/dts/bindings/clock/renesas,rx-cgc-pclk.yaml new file mode 100644 index 00000000000..ec61deb9535 --- /dev/null +++ b/dts/bindings/clock/renesas,rx-cgc-pclk.yaml @@ -0,0 +1,25 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RX Clock Control Peripheral Clock + +compatible: "renesas,rx-cgc-pclk" + +include: [clock-controller.yaml, base.yaml] + +properties: + clocks: + description: Select the clock source + + div: + type: int + required: true + description: Prescale divider to calculate the subclock frequency from the + system clock frequency. + + "#clock-cells": + const: 2 + +clock-cells: + - mstp + - stop_bit diff --git a/dts/bindings/clock/renesas,rx-cgc-pll.yaml b/dts/bindings/clock/renesas,rx-cgc-pll.yaml new file mode 100644 index 00000000000..85d515b3792 --- /dev/null +++ b/dts/bindings/clock/renesas,rx-cgc-pll.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RX Clock Generation Circuit PLL Clock + +compatible: "renesas,rx-cgc-pll" + +include: [clock-controller.yaml, base.yaml] + +properties: + clocks: + required: true + + div: + required: true + type: int + + mul: + required: true + type: int + + "#clock-cells": + const: 0 diff --git a/dts/bindings/clock/renesas,rx-cgc-root-clock.yaml b/dts/bindings/clock/renesas,rx-cgc-root-clock.yaml new file mode 100644 index 00000000000..e46d367d101 --- /dev/null +++ b/dts/bindings/clock/renesas,rx-cgc-root-clock.yaml @@ -0,0 +1,49 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +description: Renesas RX Root Clock Generation Circuit + +compatible: "renesas,rx-cgc-root-clock" + +include: [fixed-clock.yaml, base.yaml] + +properties: + mosel: + type: int + enum: + - 0 + - 1 + description: | + Choose the way for external Clock Oscillator supply + 0: Resonator + 1: External clock input + + stabilization-time: + type: int + enum: + - 0 # Wait time = 2 cycles (0.5 μs) + - 1 # Wait time = 1024 cycles (256 μs) + - 2 # Wait time = 2048 cycles (512 μs) + - 3 # Wait time = 4096 cycles (1.024 ms) + - 4 # Wait time = 8192 cycles (2.048 ms) + - 5 # Wait time = 16384 cycles (4.096 ms) + - 6 # Wait time = 32768 cycles (8.192 ms) + - 7 # Wait time = 65536 cycles (16.384 ms) + description: | + Setting for main clock oscillator wait time + + sub-clk-osc: + type: int + default: 500 + description: | + Sub-Clock stabilization time in milliseconds + + drive-capacity: + type: int + enum: + - 0 + - 1 + description: | + Drive Capacity Control (for Sub-Clock Oscillator only) + 0: Drive capacity for standard CL. + 1: Drive capacity for low CL. diff --git a/dts/rx/renesas/r5f513083xfb.dtsi b/dts/rx/renesas/r5f513083xfb.dtsi index 663be86ea4a..5f12b77fc56 100644 --- a/dts/rx/renesas/r5f513083xfb.dtsi +++ b/dts/rx/renesas/r5f513083xfb.dtsi @@ -9,30 +9,43 @@ / { clocks: clocks { - xtal: clock-xtal { - compatible = "renesas,rx-cgc-external-clock"; + #address-cells = <1>; + #size-cells = <1>; + + xtal: clock-main-osc { + compatible = "renesas,rx-cgc-root-clock"; clock-frequency = ; + mosel = <0>; + stabilization-time = <4>; #clock-cells = <0>; status = "disabled"; }; hoco: clock-hoco { - compatible = "fixed-clock"; + compatible = "renesas,rx-cgc-root-clock"; clock-frequency = ; #clock-cells = <0>; status = "okay"; }; loco: clock-loco { - compatible = "fixed-clock"; + compatible = "renesas,rx-cgc-root-clock"; clock-frequency = ; #clock-cells = <0>; status = "okay"; }; subclk: clock-subclk { - compatible = "renesas,rx-cgc-subclk"; + compatible = "renesas,rx-cgc-root-clock"; clock-frequency = <32768>; + drive-capacity = <0>; + #clock-cells = <0>; + status = "disabled"; + }; + + iwdtlsclk: clock-iwdt-low-speed { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = <15000>; #clock-cells = <0>; status = "disabled"; }; @@ -40,47 +53,99 @@ pll: pll { compatible = "renesas,rx-cgc-pll"; #clock-cells = <0>; - - /* PLL */ - source = ; - div = ; - mul = <8 0>; + div = <2>; + clocks = <&xtal>; + mul = ; + status = "disabled"; }; - pclkblock: pclkblock { + pclkblock: pclkblock@80010 { compatible = "renesas,rx-cgc-pclk-block"; + reg = <0x00080010 4>, <0x00080014 4>, <0x00080018 4>, + <0x0008001C 4>; + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD"; #clock-cells = <0>; - sysclock-src = ; + clocks = <&pll>; status = "okay"; iclk: iclk { compatible = "renesas,rx-cgc-pclk"; - clk_div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,rx-cgc-pclk"; - clk_div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,rx-cgc-pclk"; - clk_div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,rx-cgc-pclk"; - clk_div = ; + div = <1>; #clock-cells = <2>; status = "okay"; }; }; + + clkout: clkout { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&xtal>; + div = <1>; + #clock-cells = <2>; + status = "disabled"; + }; + + rtcsclk: rtcsclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&subclk>; + #clock-cells = <2>; + status = "disabled"; + }; + + caclclk: caclclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&loco>; + #clock-cells = <2>; + status = "disabled"; + }; + + cacmclk: cacmclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&xtal>; + #clock-cells = <2>; + status = "disabled"; + }; + + cachclk: cachclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&hoco>; + #clock-cells = <2>; + status = "disabled"; + }; + + cacsclk: cacsclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&subclk>; + #clock-cells = <2>; + status = "disabled"; + }; + + iwdtclk: iwdtclk { + compatible = "renesas,rx-cgc-pclk"; + clocks = <&iwdtlsclk>; + #clock-cells = <2>; + status = "disabled"; + }; }; soc { diff --git a/dts/rx/renesas/rx-qemu.dtsi b/dts/rx/renesas/rx-qemu.dtsi index 912c0c4cac2..8cbfc2c6608 100644 --- a/dts/rx/renesas/rx-qemu.dtsi +++ b/dts/rx/renesas/rx-qemu.dtsi @@ -40,6 +40,96 @@ reg-names = "IR", "IER", "IPR", "FIR"; }; + clocks: clocks { + #address-cells = <1>; + #size-cells = <1>; + + xtal: clock-main-osc { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = ; + mosel = <0>; + stabilization-time = <4>; + #clock-cells = <0>; + status = "disabled"; + }; + + hoco: clock-hoco { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "okay"; + }; + + loco: clock-loco { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = ; + #clock-cells = <0>; + status = "okay"; + }; + + subclk: clock-subclk { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = <32768>; + drive-capacity = <0>; + #clock-cells = <0>; + status = "disabled"; + }; + + iwdtlsclk: clock-iwdt-low-speed { + compatible = "renesas,rx-cgc-root-clock"; + clock-frequency = <15000>; + #clock-cells = <0>; + status = "disabled"; + }; + + pll: pll { + compatible = "renesas,rx-cgc-pll"; + #clock-cells = <0>; + div = <2>; + clocks = <&xtal>; + mul = ; + status = "disabled"; + }; + + pclkblock: pclkblock@80010 { + compatible = "renesas,rx-cgc-pclk-block"; + reg = <0x00080010 4>, <0x00080014 4>, <0x00080018 4>, + <0x0008001C 4>; + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD"; + #clock-cells = <0>; + clocks = <&pll>; + status = "okay"; + + iclk: iclk { + compatible = "renesas,rx-cgc-pclk"; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + + fclk: fclk { + compatible = "renesas,rx-cgc-pclk"; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkb: pclkb { + compatible = "renesas,rx-cgc-pclk"; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + + pclkd: pclkd { + compatible = "renesas,rx-cgc-pclk"; + div = <1>; + #clock-cells = <2>; + status = "okay"; + }; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -82,6 +172,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x00088000 0x02>; + clocks = <&pclkb MSTPA 15>; reg-names = "CMSTR0"; status = "okay"; diff --git a/include/zephyr/drivers/clock_control/renesas_rx_cgc.h b/include/zephyr/drivers/clock_control/renesas_rx_cgc.h new file mode 100644 index 00000000000..19f196b6d65 --- /dev/null +++ b/include/zephyr/drivers/clock_control/renesas_rx_cgc.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RX_CGC_H_ +#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RX_CGC_H_ + +#include +#include + +#define RX_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)) + +#define RX_CGC_CLK_SRC(node_id) \ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \ + (UTIL_CAT(RX_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \ + (RX_CLOCKS_CLOCK_DISABLED)) + +struct clock_control_rx_pclk_cfg { + const struct device *clock_src_dev; + uint32_t clk_div; +}; + +struct clock_control_rx_subsys_cfg { + uint32_t mstp; + uint32_t stop_bit; +}; + +struct clock_control_rx_pll_cfg { + const struct device *clock_dev; +}; + +struct clock_control_rx_pll_data { + uint32_t pll_div; + uint32_t pll_mul; +}; + +struct clock_control_rx_root_cfg { + uint32_t rate; +}; + +#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RX_CGC_H_ */ diff --git a/include/zephyr/dt-bindings/clock/rx_clock.h b/include/zephyr/dt-bindings/clock/rx_clock.h new file mode 100644 index 00000000000..cab40d575fd --- /dev/null +++ b/include/zephyr/dt-bindings/clock/rx_clock.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RX_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RX_H_ + +#define RX_CLOCKS_SOURCE_CLOCK_LOCO 0 +#define RX_CLOCKS_SOURCE_CLOCK_HOCO 1 +#define RX_CLOCKS_SOURCE_CLOCK_MAIN_OSC 2 +#define RX_CLOCKS_SOURCE_CLOCK_SUBCLOCK 3 +#define RX_CLOCKS_SOURCE_PLL 4 +#define RX_CLOCKS_SOURCE_CLOCK_DISABLE 0xff + +#define RX_PLL_MUL_4 7 +#define RX_PLL_MUL_4_5 8 +#define RX_PLL_MUL_5 9 +#define RX_PLL_MUL_5_5 10 +#define RX_PLL_MUL_6 11 +#define RX_PLL_MUL_6_5 12 +#define RX_PLL_MUL_7 13 +#define RX_PLL_MUL_7_5 14 +#define RX_PLL_MUL_8 15 + +#define MSTPA 0 +#define MSTPB 1 +#define MSTPC 2 +#define MSTPD 3 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RX_H_ */ diff --git a/soc/renesas/rx/rx130/Kconfig b/soc/renesas/rx/rx130/Kconfig index b68231bcd37..44d089487fb 100644 --- a/soc/renesas/rx/rx130/Kconfig +++ b/soc/renesas/rx/rx130/Kconfig @@ -5,3 +5,6 @@ config SOC_SERIES_RX130 select RX select CPU_RXV1 select XIP + select CLOCK_CONTROL_RENESAS_RX_CGC if CLOCK_CONTROL + select HAS_RENESAS_RX_RDP + select CLOCK_CONTROL diff --git a/soc/renesas/rx/rx130/soc.h b/soc/renesas/rx/rx130/soc.h index 39aa634c09f..490b315efb8 100644 --- a/soc/renesas/rx/rx130/soc.h +++ b/soc/renesas/rx/rx130/soc.h @@ -12,5 +12,6 @@ #define _SOC_H_ #include "reg_protection.h" +#include #endif /* _SOC_H_ */